[특허]System and method for error correction of digitized phase signals from MR/GMR head readback waveforms

[미국특허] System and method for error correction of digitized phase signals from MR/GMR head readback waveforms 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H03M-013/00 G11C-029/00
출원번호	US-0675857 (2000-09-29)
발명자 / 주소	Hassner, Martin Aureliano Rezzi, Francesco Trager, Barry Marshall
출원인 / 주소	International Business Machines Corporation
대리인 / 주소	Rogitz, John L.
인용정보	피인용 횟수 : 15 인용 특허 : 9

초록 ▼

A system and method for algebraically correcting errors in complex digitized phase signals from a magneto-resistive or giant magneto-resistive (MR/GMR) head readback waveform includes a data state machine that encodes phase symbols into data bits in accordance with, e.g., the (1, 10) constraint and a parity state machine that generates parity symbols such that a single inserted parity symbol does not violate the (1, 7) constraint in a run length limited code and furthermore the data following the insertion will not violate the (1, 10) constraint in a run length limited code. The state machines can be used as a trellis to perform maximum likelihood decoding on received coded data, thus performing soft algebraic error detection on received data. The invention thus guarantees better overall error rate performance than hard decision post processing of blocks of detected bits by a parity check matrix which is otherwise vulnerable to loss of bit synchronization at high linear density recording.

대표청구항 ▼

1. A data encoding device for encoding data to be recorded onto a magnetic recording medium, comprising: a data state machine transforming data symbols into phase modulated multibit symbols to render a data stream; and a parity state machine inserting at least one parity symbol into the data stream each N-1 phase modulated multibit symbols in accordance with a parity constraint, the data stream after parity symbol insertion satisfying a run length limited constraint, wherein N is an integer. 2. The device of claim 1, wherein the run length limited constraint is a (1, 10) constraint and the parity constraint is a (1, 7) constraint. 3. The device of claim 1, further comprising a parity calculator receiving an output from the data state machine and determining a parity satisfying the run length limited constraint, the parity calculator providing an input to the parity state machine. 4. The device of claim 1, wherein "N" is adjustable. 5. The device of claim 1, wherein the device further includes a disk controller receiving the data stream and recording the stream onto the magnetic recording medium. 6. The device of claim 1, wherein the device receives digitized phase symbols from a magnetic recording medium for decoding thereof, the device undertaking parity checking by performing integer lattice-based maximum likelihood decoding. 7. The device of claim 6, wherein the device is configured to find a nearest node on an integral lattice to at least one received digitized phase symbol, a difference between the received digitized phase symbol and the nearest integer node establishing an error. 8. A method for error correction in magnetic recording, comprising: encoding data symbols into phase modulated multibit symbols in accordance with a run length limited constraint: determining parity symbols for insertion thereof among the multibit symbols in accordance with a parity constraint such that the run length limited constraint is not violated after insertion of the parity symbols, inserting the parity symbols among the phase modulated multibit symbols; receiving digitized symbols representing bits from a recording medium; for each of at least some symbols, determining a closest integer node on a lattice; and using maximum likelihood decoding, determining that an error has occurred. 9. The method of claim 8, further comprising: converting the bits to symbols in accordance with a data recording constraint. 10. The method of claim 9, further comprising: reading parity symbols from data received from the recording medium; calculating parity check symbols in accordance with a parity constraint; and comparing the parity check symbols to the parity symbols to determine the occurrence of errors. 11. The method of claim 8, wherein the run length limited constraint is a (1, 10) constraint and the parity constraint is a (1, 7) constraint.

이 특허에 인용된 특허 (9) 인용/피인용 타임라인 분석

Jay Neil Livingston, Error correction using reliability values for data matrix.
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Hassner Martin A. (Palo Alto CA) Lang Luke C. K. (Cupertino CA) Ouchi Norman K. (San Jose CA) Schwiegelshohn Uwe (Dortmund Kirchhoerde DEX), Location dependent variable error correction processing for multi-track recording media using variable length coding mea.
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Nazari, Nersi; Vityaev, Andrei, Method and apparatus for encoding data incorporating check bits and maximum transition run constraint.
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Bessios Anthony, Method and apparatus for high-rate n/n+1 low-complexity modulation codes with adjustable codeword length and error control capability.
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Reed David E. ; Bliss William G., Parity channel code for enhancing the operation of a remod/demod sequence detector in a d=1 sampled amplitude read channel.
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McClellan Brett ; Leung Michael ; Fu Leo ; Jeon Taehyun, Parity insertion with precoder feedback in a read channel.
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Smith Ronald P. ; Saunders Oliver W., Pipelined architecture to decode parallel and serial concatenated codes.
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Hilden Hugh M. (Honolulu HI) Howe Dennis G. (Pittsford NY), Shift-correcting code system with efficient symbol-to-channel bit transformation.
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Hilden Hugh M. (Honolulu HI) Howe Dennis G. (Pittsford NY) Weldon ; Jr. Edward J. (Honolulu HI), Shift-correction code rate-enhancing parity encoding/decoding.
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[미국특허] System and method for error correction of digitized phase signals from MR/GMR head readback waveforms 원문보기