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Semiconductor integrated circuit and fabrication method thereof 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/76
  • H01L-031/036
  • H01L-031/112
출원번호 US-0967697 (2001-09-28)
우선권정보 JP-0165272 (1996-06-04)
발명자 / 주소
  • Ohtani, Hisashi
출원인 / 주소
  • Semiconductor Energy Laboratory Co., Ltd.
대리인 / 주소
    Fish & Richardson P.C.
인용정보 피인용 횟수 : 23  인용 특허 : 25

초록

A semiconductor integared circuit having a high withstand voltage TFT and a TFT which is capable of operating at high speed in a circuit of thin film transistors (TFT) and methods for fabriacting such circuits will be provided. A gate insulating film of the TFT required to operate a high speed (e.g.

대표청구항

A semiconductor integared circuit having a high withstand voltage TFT and a TFT which is capable of operating at high speed in a circuit of thin film transistors (TFT) and methods for fabriacting such circuits will be provided. A gate insulating film of the TFT required to operate a high speed (e.g.

이 특허에 인용된 특허 (25)

  1. Yudasaka Ichio (Suwa JPX) Matsuo Minoru (Suwa JPX) Takenaka Satoshi (Suwa JPX), Active matrix panel and manufacturing method including TFTs having variable impurity concentration levels.
  2. Ohhashi Masayuki (Tokyo JPX), CMOS ESD protection structure.
  3. Yamazaki Shunpei,JPX ; Zhang Hongyong,JPX, Display device with inverted type transistors in the peripheral and pixel portions.
  4. Doklan Raymond H. (Whitehall Township ; Lehigh County PA) Martin ; Jr. Edward P. (Bethlehem PA) Roy Pradip K. (Allentown PA) Shive Scott F. (Bethlehem PA) Sinha Ashok K. (Allentown PA), Fabricating a semiconductor device with low defect density oxide.
  5. Shimizu Shinji (Houya JPX) Komori Kazuhiro (Kodaira JPX) Kosa Yasunobu (Kodaira JPX) Sugiura June (Musashino JPX), Forming memory transistors with varying gate oxide thicknesses.
  6. Suzuki Masayoshi (Hitachiota JPX) Izaki Naoyuki (Hitachiota JPX), High voltage pulse generating semiconductor circuit with improved driving arrangement.
  7. Fujihira Tatsuhiko (Nagano JPX) Nishiura Masaharu (Nagano JPX), High-withstand-voltage integrated circuit for driving a power semiconductor device.
  8. Gofuku Ihachiro (Hiratsuka JPX) Osada Yoshiyuki (Atsugi JPX) Nakagawa Katsumi (Kawasaki JPX), Method for driving a photo-sensor by applying a pulse voltage to an auxiliary electrode during a non-read time.
  9. Zhang Hongyong (Kanagawa JPX) Ohnuma Hideto (Kanagawa JPX) Yamaguchi Naoaki (Kanagawa JPX) Takemura Yasuhiko (Kanagawa JPX), Method for fabricating thin film transistor using anodic oxidation.
  10. Codama Mitsufumi (Kanagawa JPX), Method for forming a MOS transistor and structure thereof.
  11. Chang Ko-Min (Austin TX) Shum Danny Pak-Chum (Austin TX) Chang Kuo-Tung (Austin TX), Method for making an EEPROM cell with isolation transistor.
  12. Tasch ; Jr. Aloysious F. (Richardson TX) Penz Perry A. (Richardson TX) Pankratz John M. (Plano TX) Lam Hon W. (Dallas TX), Method of fabricating display with semiconductor circuits on monolithic structure and flat panel display produced thereb.
  13. Konuma Toshimitsu (Kanagawa JPX) Hiroki Masaaki (Kanagawa JPX) Zhang Hongyong (Kanagawa JPX) Yamamoto Mutsuo (Kanagawa JPX) Takemura Yasuhiko (Kanagawa JPX), Method of fabricating thin film semiconductor integrated circuit.
  14. Wieder Armin (Gauting DEX) Risch Lothar (Ottobrunn DEX), Photo-transistor in MOS thin-film technology and method for production and operation thereof.
  15. Tigelaar Howard L. (Allen TX) Riemenschneider Bert R. (Plano TX) Chapman Richard A. (Dallas TX) Appel Andrew T. (Dallas TX), Process for thickening selective gate oxide regions.
  16. Koyama Jun,JPX ; Takemura Yasuhiko,JPX ; Hayakawa Masahiko,JPX ; Yamazaki Shunpei,JPX ; Miyanaga Akiharu,JPX ; Ohtani Hisashi,JPX, Semiconductor active matrix circuit.
  17. Zhang Hongyong,JPX ; Ohnuma Hideto,JPX ; Yamaguchi Naoaki,JPX ; Takemura Yasuhiko,JPX, Semiconductor device and method for fabricating the same.
  18. Mitsufumi Codama JP; Kazushi Sugiura JP; Yukio Yamauchi JP; Naoya Sakamoto JP; Michio Arai JP, Semiconductor device and method for operating the same.
  19. Okamoto Yutaka (Tokyo JPX) Yamada Makoto (Kanagawa JPX) Shinguu Masataka (Tokyo JPX), Semiconductor device and method of manufacturing same.
  20. Nozaki Masahiko,JPX, Semiconductor device and production method therefor.
  21. Suzawa Hideomi,JPX, Semiconductor device including active matrix circuit.
  22. Koyama Jun (Kanagawa JPX) Takemura Yasuhiko (Kanagawa JPX), Semiconductor integrated circuit having N-channel and P-channel transistors.
  23. Natsui Yoshinobu (Tokyo JPX), Semiconductor memory device.
  24. Konuma Toshimitsu (Kanagawa JPX) Hiroki Masaaki (Kanagawa JPX) Zhang Hongyong (Kanagawa JPX) Yamamoto Mutsuo (Kanagawa JPX) Takemura Yasuhiko (Kanagawa JPX), Thin film semiconductor integrated circuit and method of fabricating the same.
  25. Kodaira Toshimoto (Suwa JPX) Oshima Hiroyuki (Suwa JPX) Mano Toshihiko (Suwa JPX), Thin film transistor and display device including same.

이 특허를 인용한 특허 (23)

  1. Ohtani, Hisashi, Camera having display device utilizing TFT.
  2. Lin, Mou-Shiung; Lin, I, Shih-Hsiung, Chip package having a chip combined with a substrate via a copper pillar.
  3. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip package with die and substrate.
  4. Lin, Mou-Shiung, High performance sub-system design and assembly.
  5. Lee, Jin-Yaun; Lin, Mou-Shiung; Huang, Ching-Cheng, Integrated chip package structure using ceramic substrate and method of manufacturing the same.
  6. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using organic substrate and method of manufacturing the same.
  7. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using silicon substrate and method of manufacturing the same.
  8. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Method for fabricating chip package with die and substrate.
  9. Yamazaki, Shunpei; Arai, Yasuyuki; Koyama, Jun, Semiconductor device and fabrication method thereof.
  10. Yamazaki, Shunpei; Arai, Yasuyuki; Koyama, Jun, Semiconductor device and fabrication method thereof.
  11. Yamazaki, Shunpei; Arai, Yasuyuki; Koyama, Jun, Semiconductor device and fabrication method thereof.
  12. Tokunaga, Hajime, Semiconductor device and manufacturing method thereof.
  13. Tokunaga, Hajime, Semiconductor device and manufacturing method thereof.
  14. Tokunaga, Hajime, Semiconductor device and manufacturing method thereof.
  15. Arao,Tatsuya, Semiconductor device and method for manufacturing the same.
  16. Yamazaki, Shunpei; Arai, Yasuyuki; Koyama, Jun, Semiconductor device comprising a pixel unit including an auxiliary capacitor.
  17. Ohtani, Hisashi, Semiconductor device having display device.
  18. Ohtani, Hisashi, Semiconductor device having display device.
  19. Ohtani,Hisashi, Semiconductor device having display device.
  20. Yamazaki, Shunpei; Koyama, Jun; Arai, Yasuyuki; Kuwabara, Hideaki, Semiconductor device having stick drivers and a method of manufacturing the same.
  21. Ohtani, Hisashi, Semiconductor integrated circuit and fabrication method thereof.
  22. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Semiconductor package with interconnect layers.
  23. Lin, Mou-Shiung; Lin, Shih-Hsiung; Lo, Hsin-Jung; Chen, Ying-Chih; Chou, Chiu-Ming, Stacked chip package with redistribution lines.
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