초록 ▼

A reconfigurable computer system based on programmable logic is provided. A system design language may be used to write applications. The applications may be automatically partitioned into software components and programmable logic resource components. A virtual computer operating system may be prov

A reconfigurable computer system based on programmable logic is provided. A system design language may be used to write applications. The applications may be automatically partitioned into software components and programmable logic resource components. A virtual computer operating system may be provided to schedule and allocate system resources. The virtual computer operating system may include a virtual logic manager that may increase the capabilities of programmable logic resources in the system.

대표청구항 ▼

A reconfigurable computer system based on programmable logic is provided. A system design language may be used to write applications. The applications may be automatically partitioned into software components and programmable logic resource components. A virtual computer operating system may be prov

A reconfigurable computer system based on programmable logic is provided. A system design language may be used to write applications. The applications may be automatically partitioned into software components and programmable logic resource components. A virtual computer operating system may be provided to schedule and allocate system resources. The virtual computer operating system may include a virtual logic manager that may increase the capabilities of programmable logic resources in the system. pace; data storage; and an instruction sequencing unit, coupled to said data storage and said execution resources, that supplies instructions within said data storage to said plurality of load-store units, said instruction sequencing unit including a dispatch unit that hashes a target address indicated by a memory access instruction to determine a particular subset among said plurality of disjoint subsets of address space to which said target address belongs and that dispatches the memory access instruction for execution to a particular load-store unit among said plurality of load-store units that processes memory access instructions having target addresses belonging to said particular subset. 6. The data processing system of claim 5, wherein a maximum number of instructions that can be concurrently executed is different for first and second load-store units among said plurality of load-store units. 7. The data processing system of claim 5, wherein a first load-store unit among said plurality of load-store units executes only instructions accessing integer data and a second load-store unit among said plurality of load-store units executes only instructions accessing floating-point data. 8. The data processing system of claim 5, said data storage comprising a cache subsystem including a plurality of caches that store data utilized by said execution resources, wherein each cache among said plurality of caches stores only data having associated addresses within a respective one of said plurality of subsets of said address space. 9. The data processing system of claim 8, wherein said plurality of caches are at a same level of said cache subsystem. 10. The data processing system of claim 9, wherein said plurality of caches comprise a first plurality of caches, said data processing system further comprising a second plurality of caches that each store only data within a respective one of said plurality of subsets of the address space. 11. The data processing system of claim 5, wherein said at least one interconnect comprises a plurality of interconnects coupled to said at least one processor, wherein each of said plurality of interconnects conveys transactions for data associated with a respective one of said plurality of subsets of the address space. 12. The data processing system of claim 11, said at least one system memory comprising a plurality of system memories that are each coupled to a respective one of said plurality of interconnects, wherein each of said plurality of system memories stores only data having associated addresses within a respective one of said plurality of subsets of said address space. 13. The data processing system of claim 11, and further comprising a plurality of processors including said at least one processor, wherein each of said plurality of processors is coupled to all of said plurality of interconnects. instruction. 4. The method of claim 3, wherein the ALAT includes storage locations for a register ID, an address, and validity information associate with the advanced load instruction. 5. A machine-accessible medium that provides instructions that, if executed by a processor will cause said processor to perform operations comprising: an advanced load address table (ALAT) storing data associated with an advanced load operation; load check lookup logic accessing the ALAT in response to executing a load check instruction; an advanced load speculative pipeline storing data associated with a speculative advanced load instruction; a speculative invalidation pipeline storing data associated with a speculative invalidation instruction; and prioritization logic prioritizing between the speculative advanced load instruction, the speculative invalidation instruction, and the advanced load instruction. 6. The machine-accessible medium of claim 5, wherein the ALAT includes storage locations for a register ID, an address, and validity information associate with the advanced load instruction.