초록 ▼

A card shuffler is disclosed having a card output portion that is easily connectable to either a first output card receiver or a second output card receiver. The first output card receiver enables the dealer to remove cards one at a time from the shuffler. The second output card receiver enables the

A card shuffler is disclosed having a card output portion that is easily connectable to either a first output card receiver or a second output card receiver. The first output card receiver enables the dealer to remove cards one at a time from the shuffler. The second output card receiver enables the dealer to remove a group of cards at a time from the shuffler.

대표청구항 ▼

A card shuffler is disclosed having a card output portion that is easily connectable to either a first output card receiver or a second output card receiver. The first output card receiver enables the dealer to remove cards one at a time from the shuffler. The second output card receiver enables the

A card shuffler is disclosed having a card output portion that is easily connectable to either a first output card receiver or a second output card receiver. The first output card receiver enables the dealer to remove cards one at a time from the shuffler. The second output card receiver enables the dealer to remove a group of cards at a time from the shuffler. herein a first load-store unit among said plurality of load-store units executes only instructions accessing integer data and a second load-store unit among said plurality of load-store units executes only instructions accessing floating-point data. 4. The processor of claim 3, wherein said data storage includes a cache subsystem having a plurality of operand data caches at a same level of said cache subsystem. 5. A data processing system, comprising: at least one interconnect; at least one system memory coupled to said interconnect; and at least one processor coupled to said interconnect, wherein said processor includes: execution resources including a plurality of load-store units, wherein each load-store unit among said plurality of load-store units processes only those memory access instructions that access data having associated target addresses within a respective one of a plurality of disjoint subsets of an address space; data storage; and an instruction sequencing unit, coupled to said data storage and said execution resources, that supplies instructions within said data storage to said plurality of load-store units, said instruction sequencing unit including a dispatch unit that hashes a target address indicated by a memory access instruction to determine a particular subset among said plurality of disjoint subsets of address space to which said target address belongs and that dispatches the memory access instruction for execution to a particular load-store unit among said plurality of load-store units that processes memory access instructions having target addresses belonging to said particular subset. 6. The data processing system of claim 5, wherein a maximum number of instructions that can be concurrently executed is different for first and second load-store units among said plurality of load-store units. 7. The data processing system of claim 5, wherein a first load-store unit among said plurality of load-store units executes only instructions accessing integer data and a second load-store unit among said plurality of load-store units executes only instructions accessing floating-point data. 8. The data processing system of claim 5, said data storage comprising a cache subsystem including a plurality of caches that store data utilized by said execution resources, wherein each cache among said plurality of caches stores only data having associated addresses within a respective one of said plurality of subsets of said address space. 9. The data processing system of claim 8, wherein said plurality of caches are at a same level of said cache subsystem. 10. The data processing system of claim 9, wherein said plurality of caches comprise a first plurality of caches, said data processing system further comprising a second plurality of caches that each store only data within a respective one of said plurality of subsets of the address space. 11. The data processing system of claim 5, wherein said at least one interconnect comprises a plurality of interconnects coupled to said at least one processor, wherein each of said plurality of interconnects conveys transactions for data associated with a respective one of said plurality of subsets of the address space. 12. The data processing system of claim 11, said at least one system memory comprising a plurality of system memories that are each coupled to a respective one of said plurality of interconnects, wherein each of said plurality of system memories stores only data having associated addresses within a respective one of said plurality of subsets of said address space. 13. The data processing system of claim 11, and further comprising a plurality of processors including said at least one processor, wherein each of said plurality of processors is coupled to all of said plurality of interconnects.