초록 ▼

A method of cleaning a substrate before and after an LDD implantation comprising the following sequential steps. A substrate having a gate structure formed thereover is provided. The substrate is cleaned by a wet clean process including NH4OH. An LDD implantation is performed into the substrate to f

A method of cleaning a substrate before and after an LDD implantation comprising the following sequential steps. A substrate having a gate structure formed thereover is provided. The substrate is cleaned by a wet clean process including NH4OH. An LDD implantation is performed into the substrate to form LDD implants. The substrate is cleaned by a wet clean process excluding NH4OH.

대표청구항 ▼

A method of cleaning a substrate before and after an LDD implantation comprising the following sequential steps. A substrate having a gate structure formed thereover is provided. The substrate is cleaned by a wet clean process including NH4OH. An LDD implantation is performed into the substrate to f

A method of cleaning a substrate before and after an LDD implantation comprising the following sequential steps. A substrate having a gate structure formed thereover is provided. The substrate is cleaned by a wet clean process including NH4OH. An LDD implantation is performed into the substrate to form LDD implants. The substrate is cleaned by a wet clean process excluding NH4OH. ein the cathode-wafer comprises the Cu surface, and wherein the anode comprises at least one material selected from a group consisting essentially of copper (Cu), a copper-platinum alloy (Cu--Pt), titanium (Ti), platinum (Pt), a titanium-platinum alloy (Ti--Pt), an anodized copper-zinc alloy (Cu--Zn, i.e., brass), a platinized titanium (Pt/Ti), and a platinized copper-zinc (Pt/Cu--Zn, i.e., platinized brass). 7. A method, as recited in claim 1, wherein said semiconductor substrate further comprises a barrier layer formed in the via under said Cu surface, and wherein the barrier layer comprises at least one material selected from a group consisting essentially of titanium silicon nitride (TixSiyNz), tantalum nitride (TaN), and tungsten nitride (WxNy). 8. A method, as recited in claim 7, wherein said semiconductor substrate further comprises an underlayer formed on the barrier layer, wherein said underlayer comprises at least one material selected from a group consisting essentially of tin (Sn) and palladium (Pd), and wherein said Cu surface is formed over said barrier layer and on said underlayer. 9. A method, as recited in claim 8, wherein said underlayer comprises a thickness range of approximately 15 .ANG. to approximately 50 .ANG., wherein said barrier layer comprises a thickness range of approximately 10 .ANG. to approximately 30 .ANG., wherein said Cu surface comprises a thickness range of approximately 30 .ANG. to approximately 100 .ANG., and wherein said interim Cu--Zn alloy thin film comprises a thickness range of approximately 100 .ANG. to approximately 300 .ANG.. 10. A method, as recited in claim 1, wherein the annealing steps are performed in a temperature range of approximately 150° C. to approximately 450° C., and wherein the annealing steps are performed for a duration range of approximately 0.5 minutes to approximately 60 minutes. umber of high-angle grain boundaries per area includes forming adjacent high-angle grain boundaries separated by a first distance; and, wherein forming a second number of high-angle grain boundaries per area includes forming adjacent high-angle grain boundaries separated by a second distance, greater than the first distance. 6. The method of claim 5 further comprising: forming at least one transistor including a channel region in the second area; and, forming at least one transistor including a channel region in the first area. 7. The method of claim 6 wherein forming the transistor in the second area includes completely forming a transistor channel region, having a length less than, or equal to the second distance, between adjacent high-angle grain boundaries. 8. The method of claim 7 wherein forming the transistor in the first area includes forming a transistor channel region, having a length greater than the first distance, including at least one high-angle grain boundary. 9. The method of claim 1 further comprising: selecting a plurality of masks; projecting the laser beam through each mask to anneal a corresponding area of semiconductor film; and, creating a particular condition in each area of the semiconductor film. 10. The method of claim 1 wherein projecting the laser beam through the first mask to anneal a first area of semiconductor film includes using the first mask to laser anneal a plurality of nonadjacent regions of semiconductor film; and, wherein projecting the laser beam through the second mask to anneal a second area of semiconductor film includes using the second mask to laser anneal a plurality of nonadjacent regions of semiconductor film. 11. The method of claim 10 wherein using the first mask to laser anneal a plurality of nonadjacent regions of semiconductor film includes: sequentially exposing each first area region to the projected laser beam; sequentially annealing each of the nonadjacent regions of the area. 12. The method of claim 10 further comprising: establishing an order of adjacent regions across the semiconductor film; aligning the laser beam with the semiconductor film in the established order; wherein using the first mask to laser anneal a plurality of nonadjacent regions of semiconductor film includes projecting the laser beam through the first mask when the laser beam is aligned with a first area region; and, wherein using the second mask to laser anneal a plurality of nonadjacent regions of sem