초록 ▼

By using a high purity target as a target, using a single gas, argon (Ar), as a sputtering gas, setting the substrate temperature at 300° C. or less, setting the sputtering power from 1 kW to 9 kW, and setting the sputtering gas pressure from 1.0 Pa to 3.0 Pa, the film stress of a film is made from

By using a high purity target as a target, using a single gas, argon (Ar), as a sputtering gas, setting the substrate temperature at 300° C. or less, setting the sputtering power from 1 kW to 9 kW, and setting the sputtering gas pressure from 1.0 Pa to 3.0 Pa, the film stress of a film is made from -1×1010dyn/cm2to 1×1010dyn/cm2. By thus using a conducting film in which the amount of sodium contained within the film is equal to or less than 0.03 ppm, preferably equal to or less than 0.01 ppm, and having a low electrical resistivity (equal to or less than 40 μΩ·cm), as a gate wiring material and a material for other wirings of a TFT, the operating performance and the reliability of a semiconductor device provided with the TFT can be increased.

대표청구항 ▼

By using a high purity target as a target, using a single gas, argon (Ar), as a sputtering gas, setting the substrate temperature at 300° C. or less, setting the sputtering power from 1 kW to 9 kW, and setting the sputtering gas pressure from 1.0 Pa to 3.0 Pa, the film stress of a film is made from

By using a high purity target as a target, using a single gas, argon (Ar), as a sputtering gas, setting the substrate temperature at 300° C. or less, setting the sputtering power from 1 kW to 9 kW, and setting the sputtering gas pressure from 1.0 Pa to 3.0 Pa, the film stress of a film is made from -1×1010dyn/cm2to 1×1010dyn/cm2. By thus using a conducting film in which the amount of sodium contained within the film is equal to or less than 0.03 ppm, preferably equal to or less than 0.01 ppm, and having a low electrical resistivity (equal to or less than 40 μΩ·cm), as a gate wiring material and a material for other wirings of a TFT, the operating performance and the reliability of a semiconductor device provided with the TFT can be increased. ons of transistors forming peripheral logic, said integrated circuit portion further comprising: transistor diffusion regions relative to said gate regions of said peripheral logic transistors; and silicide at the surface of said transistor diffusion regions for said peripheral logic. 5. The integrated circuit portion of claim 1, wherein said transistor diffusion regions include source and drain regions. BiCMOS Process," J. Electrochem. Soc., vol. 139, No. 2, Feb. 1992, pp. 53. Ramaswami, et al., "Polysilicon Planarization Using Spin-On Glass," J. Electrochem. Soc., vol. 139, No. 2, Feb. 1992, pp. 591-599. C.B. Zarowin, "Plasma Etch Anisotropy--Theory and Some Verifying Experiments Relating Ion Trans Ion Energy, and Etch Profiles," J. Electrochem. Soc. Solid State Science and Technology, May 1993, pp. 1144-1152. A. S