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A sound activated toy vehicle includes a body, a chassis, and a motor. The chassis accommodates the body and has at least a front wheel and a rear wheel. The motor is drivingly connected to at least one of the front wheel and the rear wheel. The toy vehicle also includes a sound transducer configure

A sound activated toy vehicle includes a body, a chassis, and a motor. The chassis accommodates the body and has at least a front wheel and a rear wheel. The motor is drivingly connected to at least one of the front wheel and the rear wheel. The toy vehicle also includes a sound transducer configured to generate an electrical signal in response to detected sound. The toy vehicle also includes a controller having an input electrically connected to the sound transducer and an output electrically connected to the motor. The controller changes the output to the motor when the electrical signal is received by the input from the sound transducer. The toy vehicle also includes a vehicle accessory having an exterior portion. The vehicle accessory is mounted for movement between a first position and a second position by mechanical power from the motor.

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A sound activated toy vehicle includes a body, a chassis, and a motor. The chassis accommodates the body and has at least a front wheel and a rear wheel. The motor is drivingly connected to at least one of the front wheel and the rear wheel. The toy vehicle also includes a sound transducer configure

A sound activated toy vehicle includes a body, a chassis, and a motor. The chassis accommodates the body and has at least a front wheel and a rear wheel. The motor is drivingly connected to at least one of the front wheel and the rear wheel. The toy vehicle also includes a sound transducer configured to generate an electrical signal in response to detected sound. The toy vehicle also includes a controller having an input electrically connected to the sound transducer and an output electrically connected to the motor. The controller changes the output to the motor when the electrical signal is received by the input from the sound transducer. The toy vehicle also includes a vehicle accessory having an exterior portion. The vehicle accessory is mounted for movement between a first position and a second position by mechanical power from the motor. wherein the mask signal forces at least a portion of input data having a programmed state to an erased state. 2. The flash memory device of claim 1 further comprising: control circuitry to control write operations to non-volatile flash memory cells of a flash memory array, wherein the control circuitry does not write input data having an erased state to the memory array. 3. The flash memory device of claim 1 further comprising: a mask logic circuit to output data having an erased state when the mask signal is asserted. 4. The flash memory device of claim 3 wherein the mask logic circuit performs an OR logic function in response to the mask signal and input data. 5. A flash memory device comprising: a plurality of non-volatile flash memory cells; a data connection to receive an input data signal for storage in at least one of the plurality of non-volatile flash memory cells; a data mask connection to receive a mask signal used to selectively mask the input data signal; and a mask logic circuit coupled to provide an output data signal in response to the input data signal and the mask signal, wherein the output data signal of the mask logic circuit provides data in a logic 1 state in response to the input data signal having a logic 1 state or the assertion of the mask signal. 6. The flash memory device of claim 5 wherein the mask logic circuit provides a logic OR function. 7. The flash memory device of claim 5 wherein the data mask connection comprises: a DQML connection, wherein DQML corresponds to a lower address data connection; and a DQMH connection, wherein DQMH corresponds to an upper address data connection. 8. A flash memory device comprising: a plurality of non-volatile flash memory cells; a DQ connection to receive input data for storage in the plurality of non-volatile flash memory cells; a DQMASK connection to receive an active high mask signal; and a mask logic circuit having a first input coupled to the DQ connection and a second input coupled to the DQMASK connection, wherein the mask logic circuit outputs data having an erased state in response to input data having an erased state or an assertion of the mask signal. 9. The flash memory device of claim 8 further comprising: a data input latch coupled between the DQ connection and the first input of the mask logic circuit. 10. The flash memory device of claim 8 further comprising: a flash memory array comprising the plurality of non-volatile flash memory cells; and a data input latch coupled between an output of the mask logic circuit and the memory array. 11. The flash memory device of claim 8 wherein the erased state is a logic 1. 12. A flash memory device comprising: a memory array having a plurality of non-volatile flash memory cells; control circuitry to control write operations to the non-volatile flash memory cells, wherein the control circuitry writes only logic 0 data to the memory array; a DQ connection to receive input data; a DQMASK connection to receive an active high mask signal; and a mask logic circuit having a first input coupled to the DQ connection and a second input coupled to the DQMASK connection, wherein the mask logic circuit outputs logic 1 data in response to input data having a logic 1 data or an assertion of the mask signal. 13. The flash memory device of claim 12 wherein the mask logic circuit performs an OR logic function. 14. The flash memory device of claim 12 further comprises: a data input logic circuit coupled between the memory array and the mask logic circuit. 15. The flash memory device of claim 12 further comprises: a data input logic circuit coupled between the DQ connection and the mask logic circuit. 16. A flash memory system comprising: a processor to provide input data; a flash memory to store the input data from the processor, the flash memory comprises memory cells arranged in columns and rows; a DQ connection coupled to receive the input data; a DQMAS