초록 ▼

A command and control system and method for multiple turbogenerators in a grid parallel system includes a master controller to start, sequence, coordinate power commands, and provide fault handling to each of the individual turbogenerators and the specific control modes. A bidirectional power meter,

A command and control system and method for multiple turbogenerators in a grid parallel system includes a master controller to start, sequence, coordinate power commands, and provide fault handling to each of the individual turbogenerators and the specific control modes. A bidirectional power meter, that measures the load consumption (or production when a turbogenerator system is installed) in a building or application, may also be utilized. This power meter can provide a reference or setpoint to the master controller for controlling the individual turbogenerators.

대표청구항 ▼

A command and control system and method for multiple turbogenerators in a grid parallel system includes a master controller to start, sequence, coordinate power commands, and provide fault handling to each of the individual turbogenerators and the specific control modes. A bidirectional power meter,

A command and control system and method for multiple turbogenerators in a grid parallel system includes a master controller to start, sequence, coordinate power commands, and provide fault handling to each of the individual turbogenerators and the specific control modes. A bidirectional power meter, that measures the load consumption (or production when a turbogenerator system is installed) in a building or application, may also be utilized. This power meter can provide a reference or setpoint to the master controller for controlling the individual turbogenerators. ing. 2. A semiconductor integrated circuit device according to claim 1, wherein: said active regions are defined by said element isolation region. 3. A semiconductor integrated circuit device according to claim 1, wherein: said dummy gate interconnections extend over said dummy region and said element isolation insulating film. 4. A semiconductor integrated circuit device according to claim 1, further comprising: interconnections each formed above said interlayer insulating film; dummy interconnections each formed of a same interconnection layer with that of said interconnections and disposed in a region spaced from said interconnections; and an insulating film covering said interconnections and dummy interconnections, said insulating film including a film planarized by polishing. 5. A device according to claim 1, wherein said dummy gate interconnections are formed also in a scribing area. 6. A device according to claim 1, wherein each gate electrode constitutes a gate electrode of a selective MISFET of a memory cell of a DRAM. 7. A semiconductor integrated circuit device according to claim 1, wherein said gate electrode extends on said element isolation region to form a gate interconnection such that said gate interconnection is formed so as not to extend over said dummy regions. 8. A semiconductor integrated circuit device comprising: an active region and a dummy region of a semiconductor substrate; a semiconductor element formed in said active region; a trench defining said active region and said dummy region; an element isolation insulating film embedded in said trench with an insulating film including a film planarized by polishing; and a gate interconnection formed on said active region and element isolation insulating film; and an element isolation region defining said active region and being comprised of said dummy region and element isolation insulating film, said gate interconnection extending over said element isolation insulating film so as not to extend over said dummy region. 9. A device according to claim 8, wherein: a dummy gate interconnection is comprised of a same layer as said gate interconnection, and said dummy gate interconnection is disposed on said dummy region and element isolation insulating film in said element isolation region. 10. A device according to claim 8, wherein said dummy region is formed also in a scribing area. 11. A semiconductor integrated circuit device according to claim 8, wherein dummy gate interconnections are comprised of a same layer as said gate interconnection and are formed over said element isolation region. 12. A semiconductor integrated circuit device comprising: interconnections formed on a principal surface of a semiconductor substrate; dummy interconnections each formed of a same interconnection layer with that of said interconnections and disposed in a region spaced from said interconnections; and an insulating film covering said interconnections and dummy interconnections and including a film planarized by polishing; said dummy interconnections being formed also in a scribing area, wherein a length of said dummy interconnection is shorter than a distance between bonding pads. 13. A semiconductor integrated circuit device comprising: a semiconductor substrate having a principal surface, said principal surface including active areas for MISFETs to be formed and an isolation area for providing a required space between said active areas; a trench pattern formed in said substrate except for said active areas such that a plurality of dummy semiconductor regions separated from each other by said trench pattern are formed at said isolation area, said trench pattern having a selected trench portion and another trench portion, said selected trench portion formed in a portion of said isolation area where a gate interconnection for said elements is to be provided, and said another trench portion formed so as to define active semi