초록 ▼

A flexible method of error coding uses at least two generating polynomials to provide different degrees of error protection and to optionally superimpose a phantom channel on a primary channel, without the need for explicit signaling from transmitter to receiver. An encoded message is CRC decoded th

A flexible method of error coding uses at least two generating polynomials to provide different degrees of error protection and to optionally superimpose a phantom channel on a primary channel, without the need for explicit signaling from transmitter to receiver. An encoded message is CRC decoded the on the receive side with at least two different generating polynomials. Based on the results of the twin decoding, the present method can determine which of the generating polynomials was used to encode the message and respond accordingly. For instance, if the a particular generating polynomial was used, then this may be use to indicate that a second channel has been superimposed onto the primary channel and that second channel may be extracted. On the other hand, if another generating polynomial, such as the default generating polynomial, was used, this may be used to indicate that no second channel has been superimposed.

대표청구항 ▼

A flexible method of error coding uses at least two generating polynomials to provide different degrees of error protection and to optionally superimpose a phantom channel on a primary channel, without the need for explicit signaling from transmitter to receiver. An encoded message is CRC decoded th

A flexible method of error coding uses at least two generating polynomials to provide different degrees of error protection and to optionally superimpose a phantom channel on a primary channel, without the need for explicit signaling from transmitter to receiver. An encoded message is CRC decoded the on the receive side with at least two different generating polynomials. Based on the results of the twin decoding, the present method can determine which of the generating polynomials was used to encode the message and respond accordingly. For instance, if the a particular generating polynomial was used, then this may be use to indicate that a second channel has been superimposed onto the primary channel and that second channel may be extracted. On the other hand, if another generating polynomial, such as the default generating polynomial, was used, this may be used to indicate that no second channel has been superimposed. coder provides plural answers for storage in the plurality of buffers, and the excess op codes provide plausible wrong answers. 19. The microprocessor of claim 1, further comprising: a capability of accepting a key shared with a compiler, the key used by the compiler to encrypt standard op codes into encrypted op codes; and data and instructions provided to a computer via program information includes an intentional introduction of errors which are correctable with error correction algorithms, said correction algorithms pre-selected according to the key. 20. The microprocessor of claim 19, further comprising: an instruction buffer which contains logic which can route a subset of the instruction bits from bit location in the buffer to destination logic gates which eventually reach a programmable instruction decoder and an instruction buffer interdependency checking logic block; and said correction algorithms pre-selected according to long instruction words and changed on a periodic basis by codes provided in the instructions gathered into the instruction buffer. 21. The microprocessor of claim 19, wherein the instruction buffer interdependency checking logic includes any combination of the following: multiplexers to select a subset of bits from a long instruction word in the instruction buffer to be logically combined to match a sequencer value; a sequencer incremented at times determined by the key and which is reset upon the occurrence of the sequencer reset code in the instruction buffer; distribution of bits for one encrypted op code across several long instruction words in the instruction buffer; distribution of several encrypted op codes around the long instruction words in the instruction buffer; a program counter which does not normally increment by one, but which increments by some other constant or variable amount determined by the serial number, the key, and the sequencer value so that encrypted op codes which will be used sequentially in time do not occur sequentially in the instruction buffer, and for which, the time sequential chosen op codes are selected by the multiplexer controlled by the key, the serial number, and the sequencer; error correction circuits controlled by the key, sequencer, and supplementary error correcting codes received from the instruction buffer by means of the multiplexers; and dependency validation codes received through the multiplexer of the instruction buffer checked by logic circuits that depend on the key, the serial number, instruction bits, and camouflage bits. 22. The microprocessor of claim 21, wherein dependency validation codes are received through the multiplexer of the instruction buffer checked by logic circuits that depend on the key, the serial number, instruction bits, and camouflage bits so that incorrect validation bits provide an alarm. 23. The microprocessor of claim 1, further comprising: a store for a key shared with a compiler, the key used by the compiler to encrypt standard op codes into encrypted op codes; and dependency validation codes received through an instruction buffer checked by logic circuits that depend on the key, a serial number, instruction bits, and camouflage bits so that incorrect validation bits provide an