초록 ▼

An improved pool cleaner is provided of the type for random travel over submerged floor and side wall surfaces of a swimming pool or the like to dislodge and collect debris. The pool cleaner includes a hydraulically contoured external housing having a stabilizer float integrated with a carrying hand

An improved pool cleaner is provided of the type for random travel over submerged floor and side wall surfaces of a swimming pool or the like to dislodge and collect debris. The pool cleaner includes a hydraulically contoured external housing having a stabilizer float integrated with a carrying handle at an elevated rearward location. The pool cleaner additionally incorporates modular components including a simplified mast unit and related water distribution manifold for delivery of water under pressure to a water turbine drive unit for rotatably driving cleaner wheels to travel over submerged pool surfaces, with a portion of the pressurized water inducing a vacuum action for collecting debris within a porous filter bag. The modular components are mounted on an internal frame which is quickly and easily accessible for service or maintenance by removal of the external housing.

대표청구항 ▼

An improved pool cleaner is provided of the type for random travel over submerged floor and side wall surfaces of a swimming pool or the like to dislodge and collect debris. The pool cleaner includes a hydraulically contoured external housing having a stabilizer float integrated with a carrying hand

An improved pool cleaner is provided of the type for random travel over submerged floor and side wall surfaces of a swimming pool or the like to dislodge and collect debris. The pool cleaner includes a hydraulically contoured external housing having a stabilizer float integrated with a carrying handle at an elevated rearward location. The pool cleaner additionally incorporates modular components including a simplified mast unit and related water distribution manifold for delivery of water under pressure to a water turbine drive unit for rotatably driving cleaner wheels to travel over submerged pool surfaces, with a portion of the pressurized water inducing a vacuum action for collecting debris within a porous filter bag. The modular components are mounted on an internal frame which is quickly and easily accessible for service or maintenance by removal of the external housing. comprising: a) placing said circuits in a first linear dimension to obtain a first placement; b) placing said circuits in a second linear dimension to obtain a second placement, wherein said second linear dimension is orthogonal to said first linear dimension; and c) assigning a two dimensional placement for said circuits by selecting for each circuit element a first coordinate from said first placement and a second coordinate from said second placement, wherein placing said circuits in said first linear dimension and said second linear dimension include assigning a linear length to each cell proportional to its cell area and scaled by a constant factor, wherein the sum of all said lengths is an interval, and wherein said interval is a desired length of placement. 2. The method as described in claim 1 further comprising: d) placing said circuits simultaneously in two dimensions, wherein said two dimensional placement is an input to said placing. 3. The method as described in claim 1 wherein said first linear dimension is parallel to an edge of a semiconductor package. 4. The method as described in claim 1 wherein said second linear dimension is parallel to an edge of a semiconductor package. 5. A method of placing electronic circuits in one dimension, the method comprising: a) assigning a linear length to each cell proportional to its cell area and scaled by a constant factor, wherein the sum of all said lengths is an interval, and wherein said interval has a beginning and an end; b) placing fixed cells at the linear location of their fixing ports; and c) placing remaining cells in available positions along said interval. 6. The method as described in claim 5 wherein said interval is the length of one side of an integrated circuit. 7. The method as described in claim 5 wherein said c) comprises: c1) placing remaining cells using a random choice in selecting one of said remaining cells from a plurality of said remaining cells. 8. The method as described in claim 5 further comprising: d) dividing said interval into a first interval and a second interval. 9. The method as described in claim 8 wherein said first interval represents substantially one half of said interval. 10. A method of placing electronic circuits in one dimension, the method comprising: a) assigning a linear length to each cell proportional to its cell area and scaled by a constant factor, wherein the sum of all said lengths is an interval, and wherein said interval has a beginning and an end; b) placing fixed cells at the linear location of their fixing ports; and c) placing remaining cells alternately in an available positions nearest to said beginning of said interval and alternately in an available position nearest to said end of said interval. 11. A method of placing electronic circuits in one dimension, the method comprising: a) assigning a linear length to each cell proportional to its cell area and scaled by a constant factor, wherein the sum of all said lengths is an interval, and wherein said interval has a beginning and an end; b) placing fixed cells at the linear location of their fixing ports; c) placing remaining cells in available positions along said interval; d) organizing said remaining cells into a priority queue; and e) selecting one of said remaining cells from said priority queue. 12. A method of placing electronic circuits in one dimension, the method comprising: a) assigning a linear length to each cell proportional to its cell area and scaled by a constant factor, wherein the sum of all said lengths is an interval, and wherein said interval has a beginning and an end; b) placing fixed cells at the linear location of their fixing ports; and c) placing remaining cells in available positions along said interval, wherein said c) comprises: c1) organizing said remaining cells into a first priority queue, a second priority queue and an unattached list; c2) selecting one of said remaining c ells from selectively said first priority queue, said second priority queue and said unattached list; and c3) placing said one of said remaining cells in an available position nearest to said beginning of said interval if said one of said remaining cells was selected from said first priority queue, placing said one of said remaining cells in an available position nearest to said end of said interval if said one of said remaining cells was selected from said second priority queue, and placing said one of said remaining cells in available position selectively in an available position nearest to said beginning of said interval and in an available position nearest to said end of said interval if both said first priority queue and said second priority queue are empty, wherein said placing results in a fixed cell. 13. The method as described in claim 12 further comprising: d) repeating said a) through c3) until all cells are placed. 14. A method of placing electronic circuits in one dimension, the method comprising: a) assigning a linear length to each cell proportional to its cell area and scaled by a constant factor, wherein the sum of all said lengths is an interval, and wherein said interval has a beginning and an end; b) placing fixed cells at the linear location of their fixing ports; c) placing remaining cells in available positions along said interval; and d) assigning a pull direction to a net attached to one of said fixed cells. 15. A method of placing electronic circuits in one dimension, the method comprising: a) assigning a linear length to each cell proportional to its cell area and scaled by a constant factor, wherein the sum of all said lengths is an interval, and wherein said interval has a beginning and an end; b) placing fixed cells at the linear location of their fixing ports; c) placing remaining cells in available positions along said interval; and d) assigning a pull value to a net attached to one of said remaining cells. 16. The method as described in claim 15 wherein said pull value of said net is given by the relationship: pull value=w/square root((number of cells attached to said net)-1), wherein said w is an optional user-defined weighting factor. 17. A method of placing electronic circuits in one dimension, the method comprising: a) assigning a linear length to each cell proportional to its cell area and scaled by a constant factor, wherein the sum of all said lengths is an interval, and wherein said interval has a beginning and an end; b) placing fixed cells at the linear location of their fixing ports; c) placing remaining cells in available positions along said interval; d) dividing said interval into a first interval and a second interval; e) computing a pull value for a net attached to one of said remaining cells; f) assigning a pull direction to said pull value as low pull if said net is attached to one of said fixed cells located within said first interval; and g) assigning a pull direction to said pull value as high pull if said net is attached to one of said fixed cells located within said second interval. 18. The method as described in claim 17 further comprising: h) computing an edge pull value for a remaining cell, wherein said edge pull value is the difference between the total high pull of all nets attached to said remaining cell less the total low pull of all nets attached said remaining cell; and i) computing an unattached pull value for said remaining cell, wherein said unattached pull value is the total pull of all nets attached to said remaining cell, wherein said nets are not attached to a fixed cell. 19. A method of placing electronic circuits in one dimension, the method comprising: a) placing cells in one dimension to produce a first placement; b) moving cells in said first placement to improve wire length, wherein said moving produces a new placement; and c) creating a data structure for determining the number of wires crossing a point in said new placement. 20. The method as described in claim 19 further comprising using a random choice in the selection of one of a plurality of cells to move. 21. The method as described in claim 19 wherein said c) comprises: c1) creating a tree data structure. 22. The method as described in claim 19 wherein said c) comprises: c1) creating a skip list data structure. 23. The method as described in claim 19 wherein said b) comprises: b1) choosing a cell at random from said first placement; b2) determining the optimal destination to relocate said cell; b3) shifting cells between the location of said cell in said first placement and said optimal destination to make room for said cell; and b4) moving said cell to said optimal destination. 24. The method as described in claim 23 further comprising: d) repeating said b1) through b4), wherein said moving produces an improved placement, wherein said improved placement is used in place of said first placement for subsequent iterations. 25. The method as described in claim 23 wherein said b2) further comprises: b2a) finding a value x which minimizes f(x)=g(x)+h(x), wherein x is a candidate destination position for a cell, wherein h(x) is a piecewise linear function describing the changes in total wire length caused by moving said cell to said position x, and g(x) is a piecewise linear function describing the changes in total wire length caused by moving the cells between said cell and said position. 26. The method as described in claim 25 wherein said finding comprises a branch and bound method. 27. A method of placing electronic circuits in one dimension, the method comprising: a) placing cells in one dimension to produce a first placement; b) clustering cells to form a super cell; and c) moving cells in said first placement to improve wire length, wherein said moving produces a new placement, wherein said b) comprises: b1) calculating the number of wires passing through every point in said first placement; b2) initializing a current range value to be empty; b3) beginning at the cell at the beginning of the placement interval; b4) adding the number of wires passing through said cell to said current range value; b5) finding the best cut point within a span of said current range value; b6) recording said best cut point as a final cut point and setting the current range value to be empty; and b7) moving to the next cell and repeating said b4) through b7). ed number of points M, if it is, a median is calculated for every K coordinate and a coordinate ndwhich has a greatest quadratic deviation is chosen as the coordinate by which the partition is divided into two smaller partitions, every point that has ndcoordinate value less or equal to the value of its median meddis put into a first child partition and all other points into a second child partition. 2. The method as described in claim 1, wherein the quadratic deviation is calculated as a median of (Xi[nd]-medd)2,i=1, 2, . . . ,k, where Xi[nd] is ndcoordinate of point Xi. 3. The method as described in claim 1, wherein processing is continued recursively for the first child partition and the second child partition until number of points in all leaf partitions becomes less than or equal to the maximally defined number of points M. 4. The method as described in claim 1, wherein making graph edges includes finding a predetermined number of points in 2Kdirections of matter. 5. The method as described in claim 4, wherein for K=2 four closest points are found in the four directions of matter, the directions of matter including right up, left up, left down and right down. 6. The method as described in claim 1, wherein making graph edges includes determining closest points for a given point A, first determining the closest point to A in its partition which has distance ref from A, then if the smallest distance from A to a child of the same node in the partitions tree is less than or equal to ref, the second child partition is examined for a closer point to A than ref and if it is not the case and the case is that the smallest distance from A to a neighbouring partition one level up in the partition tree is less then ref the same examination is applied to parent partition in the partitions tree. 7. The method as described in claim 1, wherein a reduced number of graph points is obtained by decreasing a number of components in the set of graph points until it becomes equal to a predefined specified program input parameter C. 8. The method as described in claim 1, wherein reducing a number of graph points includes: sorting edges, wherein edges el(Xs,Xe) are sorted by length in ascending order, Xsand Xcare start and end points of the edge; initializing a set of components so that every graph point is a single component Cxi; processing edges until the number of components is equal to input parameter C, wherein processing includes if size(CXs)≥size(CXe), where size of the component is the number of belonging vertexes, a new component is made of the two components by moving all vertexes which have belonged to component CXeto CXsand erasing component CXe,if it is not the case, CXsis removed and CXeexpanded. 9. A method for partitioning an integrated circuit, comprising: partitioning an input set of points into a binary tree of partitions so that each leaf partition of the binary tree has maximally a defined number of points; making graph edges for the points by connecting each point to its closest point in every of 2Ksubspaces; and factorizing number of graph points by decreasing a number of components in the set of graph points until it becomes equal to a predefined specified program input parameter C, wherein partitioning includes checking a number of points k in a current set to determine if the number is greater than the maximally defined number of points M, if it is, a median is calculated for every K coordinate and a coordinate ndwhich has a greatest quadratic deviation is chosen as the coordinate by which the partition is divided into two smaller partitions, every point that has ndcoordinate value less or equal to the val ue of its median meddis put into a first child partition and all other points into a second child partition. 10. The method as described in claim 9, wherein the quadratic deviation is calculated as a median of (Xi[nd]-medd)2,i=1, 2, . . . ,k, where Xi[nd] is ndcoordinate of point Xi. 11. The method as described in claim 9, wherein processing is continued recursively for the first child partition and the second child partition until number of points in all leaf partitions becomes less than or equal to the maximally defined number of points M. 12. The method as described in claim 9, wherein making graph edges includes finding a maximum of 2Kclosest points in 2Kdirections of matter. 13. The method as described in claim 12, wherein for K=2 four closest points are found in the four directions of matter, the directions of matter including right up, left up, left down and right down. 14. The method as described in claim 9, wherein making graph edges includes determining closest points for a given point A, first determining the closest point to A in its partition which has distance ref from A, then if the smallest distance from A to a child of the same node in the partitions tree is less than or equal to ref, the second child partition is examined for a closer point to A than ref and if it is not the case and the case is that the smallest distance from A to a neighbouring partition one level up in the partition tree is less then ref the same examination is applied to parent partition in the partitions tree. 15. The method as described in claim 9, wherein reducing a number of graph points includes: sorting edges, wherein edges el(Xs,Xe) are sorted by length in ascending order, Xsand Xeare start and end points of the edge; initializing a set of components so that every graph point is a single component CXi; processing edges until the number of components is equal to input parameter C, wherein processing includes if size(CXs)≥size(CXe), where size of the component is the number of belonging vertexes, a new component is made of the two components by moving all vertexes which have belonged to component CXeto CXsand erasing component CXe,if it is not the case, CXsis removed and CXeexpanded. 16. A system, comprising: a memory suitable for storing a program of instructions; and a processor communicatively coupled to the memory, the processor suitable for performing a program of instructions, wherein the program of instructions configures the processor to partition an input set of points into a binary tree of partitions so that each leaf partition of the binary tree has maximally a defined number of points; making graph edges for the points by connecting each point to its closest point in every of 2Ksubspaces; and factorize number of graph points by decreasing a number of components in the set of graph points until it becomes equal to a predefined specified program input parameter C, wherein partitioning includes checking a number of points k in a current partition to determine if the number is greater than the maximally defined number of points M, if it is, a median is calculated for every K coordinate and a coordinate ndwhich has a greatest quadratic deviation is chosen as the coordinate by which the partition is divided into two smaller partitions, every point that has ndcoordinate value less or equal to the value of its median meddis put into a first child partition and all other points into a second child partition. 17. The system as described in claim 16, wherein the quadratic deviation is calculated as a median of (Xi[nd]-medd)2,i=1, 2, . . . ,k, where Xi[n d] is ndcoordinate of point Xi. 18. The system as described in claim 16, wherein processing is continued recursively for the first child partition and the second child partition until number of points in all leaf partitions becomes less than or equal to the maximally defined number of points M. 19. The system as described in claim 16, wherein making graph edges includes finding a predetermined number of points in 2Kdirections of matter. 20. The system as described in claim 19, wherein for K=2 four closest points are found in the four directions of matter, the directions of matter including right up, left up, left down and right down. 21. The system as described in claim 16, wherein making graph edges includes determining closest points for a given point A, first determining the closest point to A in its partition which has distance ref from A, then if the smallest distance from A to a child of the same node in the partitions tree is less than or equal to ref, the second child partition is examined for a closer point to A than ref and if it is not the case and the case is that the smallest distance from A to a neighbouring partition one level up in the partition tree is less then ref the same examination is applied to parent partition in the partitions tree. 22. The system as described in claim 16, wherein reducing a number of graph points includes: sorting edges, wherein edges el(Xs,Xe) are sorted by length in ascending order, Xsand Xeare start and end points of the edge; initializing a set of components so that every graph point is a single component Cxi; processing edges until the number of components is equal to input parameter C, wherein processing includes if size(CXs)≥size(CXe), where size of the component is the number of belonging vertexes, a new component is made of the two components by moving all vertexes which have belonged to component CXeto CXsand erasing component CXe,if it is not the case, CXsis removed and CXeexpanded. 23. A system for partitioning an integrated circuit, comprising: a means for partitioning an input set of points into a binary tree of partitions so that each leaf partition has maximally a defined number of points; a means for making graph edges for the points, the graph edge means communicatively coupled to the partitioning means, wherein the graph edges means connects each point to maximum 2Kclosest points to make edges of the graph; and a means for reducing number of graph points communicatively coupled to the graph edge means, wherein the reducing means decreasing a number of components in the set of graph points until it becomes equal to a predefined specified program input parameter C, wherein partitioning includes checking a number of points k in a current partition to determine if the number is greater than the maximally defined number of points M, if it is, a median is calculated for every K coordinate and a coordinate ndwhich has a greatest quadratic deviation is chosen as the coordinate by which the partition is divided into two smaller partitions, every point that has ndcoordinate value less or equal to the value of its median meddis put into a first child partition and all other points into a second child partition.