초록 ▼

The present invention provides for cooling a plurality of racked electronic devices having a first electronic device having at least one cooling vent at a first end and a plurality of cooling holes at a top, each of the cooling vents having a cooling fan, means for flowing air through the cooling ve

The present invention provides for cooling a plurality of racked electronic devices having a first electronic device having at least one cooling vent at a first end and a plurality of cooling holes at a top, each of the cooling vents having a cooling fan, means for flowing air through the cooling vent, means for outputting the air flow through a plurality of cooling holes on the top of the first electronic device. The present invention further provides for a second electronic device having a plurality of heat sink fins on the bottom. The bottom of the second electronic device coupled to the top of said first electronic device, means for aligning the plurality of cooling holes under the plurality of heat sink fins, and means for outputting the air through an output of the heat sink fins.

대표청구항 ▼

The present invention provides for cooling a plurality of racked electronic devices having a first electronic device having at least one cooling vent at a first end and a plurality of cooling holes at a top, each of the cooling vents having a cooling fan, means for flowing air through the cooling ve

The present invention provides for cooling a plurality of racked electronic devices having a first electronic device having at least one cooling vent at a first end and a plurality of cooling holes at a top, each of the cooling vents having a cooling fan, means for flowing air through the cooling vent, means for outputting the air flow through a plurality of cooling holes on the top of the first electronic device. The present invention further provides for a second electronic device having a plurality of heat sink fins on the bottom. The bottom of the second electronic device coupled to the top of said first electronic device, means for aligning the plurality of cooling holes under the plurality of heat sink fins, and means for outputting the air through an output of the heat sink fins. th a metal. 19. The photodetector of claim 10, wherein said via is for fiber alignment to an optoelectronic device. 20. A photodetector, comprising: a substrate; a buried insulator formed on said substrate; a semiconductor-on-insulator (SOI) layer formed on said substrate; alternating n-type and p-type doped fingers formed in said SOI layer; and a via formed in said substrate for backside illumination, and for fiber alignment, wherein the via is defined by a set of crystallographic planes. 21. A chip, comprising: a chip substrate; and a photodetector according to claim 1 formed on said chip substrate. 22. The chip of claim 21, further comprising: a circuit, formed on said substrate, for receiving an output from said photodetector. 23. The chip of claim 21, wherein said chip comprises a complementary metal oxide semiconductor (CMOS) chip. 24. The chip of claim 21, wherein said chip comprises a bipolar chip. 25. The chip of claim 21, wherein said chip comprises a BiCMOS chip. 26. An optoelectronic device, comprising: a substrate having a via for alignment of a fiber thereto; a buried insulator fanned on said substrate; a semiconductor-on-insulator (SOI) layer formed on said substrate; and alternating n-type and p-type doped fingers fanned in said SOI layer, wherein said via is defined by a set of crystallographic planes. 27. The optoelectronic device of claim 26, wherein said crystallographic planes comprise semiconductor 111 planes. 28. The optoelectronic device of claim 26, wherein sidewalls and a shape of the via are nondependent on an etch time of said via. 29. The photodetector of claim 1, wherein said buried mirror also functions as a bottom contact to one of said p-type doped fingers and said n-type doped fingers. 30. The photodetector of claim 1, wherein the buried mirror and the backside contact comprise a same component. 31. The photodetector of claim 1, wherein said buried mirror and said backside contact comprise a single layer. 32. The photodetector of claim 1, wherein said buried insulator isolates the backside contact from the substrate. 33. The photodetector of claim 1, wherein said doped fingers form a lateral p-i-n junction. 34. The photodetector of claim 33, wherein said lateral p-i-n junction is perpendicular to a surface of the substrate. 35. The photodetector of claim 33, wherein said photodiode comprises a lateral p-i-n diode where a p-n junction is perpendicular to an upper surface of the substrate, such that light absorption is decoupled from collection of photo-generated carriers. 36. The photodetector of claim 1, wherein said substrate comprises a single-crystal semiconductor for high-speed optical communications by said photodetector. 37. The photodetector of claim 10, wherein said mirror is corrugated on a single surface. 38. The photodetector of claim 10, wherein said mirror includes a roughened, corrugated surface on a surface furthest from said substrate, and a substantially flat surface on its surface closest to said substrate. 39. The photodetector of claim 10, wherein a surface of said insulator layer is substantially flat. 40. The photodetector of claim 10, wherein said corrugated mirror has an irregular pitch, and a randomness in spacing and shapes of features forming the corrugation. 41. The photodetector of claim 14, wherein said corrugated mirror has a non-periodic structure. 42. The photodetector of claim 10, wherein said mirror comprises a diffusive mirror. 43. The photodetector of claim 10, wherein the doped fingers form a lateral p-i-n junction which is perpendicular to a surface of the substrate.