초록 ▼

A semiconductor device manufacturing apparatus which uses a thermal CVD reaction to deposit a film onto a substrate has a ring with an electrode terminal that makes contact with either the substrate or the deposited film thereon, a power supply that applies a current or a potential to this electrode

A semiconductor device manufacturing apparatus which uses a thermal CVD reaction to deposit a film onto a substrate has a ring with an electrode terminal that makes contact with either the substrate or the deposited film thereon, a power supply that applies a current or a potential to this electrode terminal of the ring, and a piston cylinder mechanism for moving the ring up and down, so as to cause its electrode terminal to make and break contact with the substrate or deposited film thereon.

대표청구항 ▼

A semiconductor device manufacturing apparatus which uses a thermal CVD reaction to deposit a film onto a substrate has a ring with an electrode terminal that makes contact with either the substrate or the deposited film thereon, a power supply that applies a current or a potential to this electrode

A semiconductor device manufacturing apparatus which uses a thermal CVD reaction to deposit a film onto a substrate has a ring with an electrode terminal that makes contact with either the substrate or the deposited film thereon, a power supply that applies a current or a potential to this electrode terminal of the ring, and a piston cylinder mechanism for moving the ring up and down, so as to cause its electrode terminal to make and break contact with the substrate or deposited film thereon. nsation circuit comprising: an array of compensation regions configured for determining an amount of leakage current, for providing a compensation current for offsetting the leakage current within the amplifier circuit, and for injecting said compensation current into said amplifier circuit, said array of compensation regions comprising a plurality of leakage PN semiconductor regions, wherein said array of compensation regions comprise a plurality of PN leakage elements configured in parallel to provide said compensation current, and wherein at least one of said plurality of PN leakage elements comprise an area and perimeter approximate to an area and perimeter of a leakage element with the amplifier circuit. 2. The current leakage compensation circuit according to claim 1, wherein said current leakage compensation circuit further comprises a current mirror circuit configured for Injecting said compensation current to the amplifier circuit. 3. The current leakage compensation circuit according to claim 1, wherein said array of compensation regions comprise at least one PN leakage element configured to provide said compensation current. 4. The current leakage compensation circuit according to claim 1, wherein said array of compensation regions comprise at least one current source configured to provide said compensation current. 5. A current leakage compensation circuit configured for compensation of leakage current within an amplifier circuit, said current leakage compensation circuit comprising: an array of compensation regions configured for determining an amount of leakage current, for providing a compensation current for offsetting the leakage current within the amplifier circuit, and for injecting said compensation current into said amplifier circuit, said array of compensation regions comprising a plurality of leakage PN semiconductor regions, wherein said array of compensation regions comprise a plurality of PN leakage elements configured in parallel to provide said compensation current, and wherein said plurality of PN leakage elements are scaled in size to provide said compensation current. 6. A current leakage compensation circuit configured for compensation of leakage current within an amplifier circuit, said current leakage compensation circuit comprising: an array of compensation regions configured for determining an amount of leakage current, for providing a compensation current for offsetting the leakage current within the amplifier circuit, and for injecting said compensation current into said amplifier circuit, said array of compensation regions comprising a plurality of leakage PN semiconductor regions, wherein said array of compensation regions comprise at least one PN leakage element configured to provide said compensation current; and wherein said array of compensation regions comprise at least one adjustable element coupled in series with said at least one PN leakage element to facilitate adjustments to said compensation current. 7. The current leakage compensation circuit according to claim 6, wherein said array of compensation regions comprises a plurality of adjustable elements, each of said plurality of adjustable elements coupled in series with a corresponding one of said plurality of PN leakage elements to facilitate adjustments to said compensation current. 8. The current leakage compensation circuit according to claim 7, wherein said plurality of adjustable elements comprises a trimmable array that allows trimming of said compensation current. 9. The current leakage compensation circuit according to claim 2, wherein said current mirror circuit Is coupled between an output of said array of compensation regions and a compensation node configured with the amplifier circuit. 10. The current leakage compensation circuit according to claim 9, wherein said current mirror circuit comprises a plurality of current mirrors coupled between said output of said array of compensation regions