[특허]Epitaxial edge termination for silicon carbide Schottky devices and methods of fabricating silicon carbide devices incorporating same

Epitaxial edge termination for silicon carbide Schottky devices and methods of fabricating silicon carbide devices incorporating same 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-021/338
출원번호	US-0264135 (2002-10-03)
발명자 / 주소	Singh, Ranbir
출원인 / 주소	Cree, Inc.
대리인 / 주소	Myers Bigel Sibley & Sajovec, P.A.
인용정보	피인용 횟수 : 35 인용 특허 : 31

초록 ▼

대표청구항 ▼

Edge termination for a silicon carbide Schottky rectifier is provided by including a silicon carbide epitaxial region on a voltage blocking layer of the Schottky rectifier and adjacent a Schottky contact of the silicon carbide Schottky rectifier. The silicon carbide epitaxial layer may have a thickness and a doping level so as to provide a charge in the silicon carbide epitaxial region based on the surface doping of the blocking layer. The silicon carbide epitaxial region may form a non-ohmic contact with the Schottky contact. The silicon carbide epitaxial region may have a width of from about 1.5 to about 5 times the thickness of the blocking layer. Schottky rectifiers with such edge termination and methods of fabricating such edge termination and such rectifiers are also provided. Such methods may also advantageously improve the performance of the resulting devices and may simplify the fabrication process. 1. A method for fabricating a thin film transistor comprising: providing a planar substrate; forming over the planar substrate a topographic first gate electrode; forming upon the topographic first gate electrode a first gate dielectric layer; forming separated by the first gate electrode and the first gate dielectric layer a pair of source/drain layers; forming upon the pair of source/drain layers and the first gate dielectric layer a semiconductor channel layer which forms a recess with respect to the pair of source/drain layers; forming upon the semiconductor channel layer a second gate dielectric layer; and forming upon the second gate dielectric layer and also separating the pair of source/drain layers a second gate electrode, wherein: the pair of source/drain layers is formed in a self-aligned fashion with respect to the first gate electrode; and the second gate electrode is formed in a self-aligned fashion with respect to the pair of source/drain layers and the first gate electrode. 2. The method of claim 1 wherein the planar substrate is an insulator substrate. 3. The method of claim 1 wherein each of the first gate electrode and the second gate electrode is formed of a silicon material selected from the group consisting of amorphous silicon materials and polycrystalline silicon materials. 4. The method of claim 1 wherein each of the source/drain layers is formed of a silicon-germanium alloy material. 5. The method of claim 4 wherein the silicon-germanium alloy material has a germanium content of from about 10 to about 30 atomic percent. 6. The method of claim 1 wherein the semiconductor channel layer is formed of a silicon material and not a silicon-germanium alloy material. 7. The method of claim 6 wherein the semiconductor channel layer is formed to a thickness of from about 250 to about 350 angstroms. 8. A method for fabricating a thin film transistor comprising: providing a planar substrate; forming over the planar substrate a topographic first gate electrode; forming conformally upon the topographic first gate electrode a first gate dielectric layer; forming conformally upon the first gate dielectric layer a planarizing stop layer; forming upon the planarizing stop layer a silicon-germanium alloy material layer; planarizing the silicon-germanium alloy material layer to reach the planarizing stop layer and form a pair of source/drain layers separated by the topographic first gate electrode; stripping from over the first gate dielectric layer a portion of the planarizing stop layer to expose a portion of the first gate dielectric layer; forming conformally upon exposed portions of the pair of source/drain layers and the first gate dielectric layer a semiconductor channel layer which forms a recess with respect to the pair of source/drain layers; forming conformally upon the semiconductor channel layer a second gate dielectric layer; forming upon the second gate dielectric layer a second gate electrode material layer; and planarizing the second gate electrode material layer to form a second gate electrode within the recess defined by the pair of source/drain layers. 9. The method of claim 8 wherein the planar substrate is an insulator substrate. 10. The method of claim 8 wherein each of the first gate electrode and the second gate electrode is formed of a silicon material selected from the group consisting of amorphous silicon materials and polycrystalline silicon materials. 11. The method of claim 8 wherein the semiconductor channel layer is formed of a silicon material and not a silicon-germanium alloy material. 12. The method of claim 11 wherein the semiconductor channel layer is formed to a thickness of from about 250 to about 350 angstroms. 13. The method of claim 8 wherein the silicon-germanium alloy material has a germanium content of from about 10 to about 30 percent.

이 특허에 인용된 특허 (31)

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Palmour John W. (Raleigh NC), Metal-insulator-semiconductor capacitor formed on silicon carbide.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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Epitaxial edge termination for silicon carbide Schottky devices and methods of fabricating silicon carbide devices incorporating same 원문보기

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Epitaxial edge termination for silicon carbide Schottky devices and methods of fabricating silicon carbide devices incorporating same 원문보기

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