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A temperature sensor circuit includes a temperature detecting circuit, a preset value storing circuit, and a current supplying circuit. The temperature detecting circuit is configured to generate a first temperature voltage in accordance with an ambient temperature and a current. The preset value st

A temperature sensor circuit includes a temperature detecting circuit, a preset value storing circuit, and a current supplying circuit. The temperature detecting circuit is configured to generate a first temperature voltage in accordance with an ambient temperature and a current. The preset value storing circuit stores a second temperature voltage preset for a predetermined ambient temperature as a digital value. The current supplying circuit supplies the current to the temperature detecting circuit. The current supplying circuit supplies the current such that the first temperature voltage generated by the temperature detecting circuit at the predetermined ambient temperature is equal to the second temperature voltage.

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A temperature sensor circuit includes a temperature detecting circuit, a preset value storing circuit, and a current supplying circuit. The temperature detecting circuit is configured to generate a first temperature voltage in accordance with an ambient temperature and a current. The preset value st

A temperature sensor circuit includes a temperature detecting circuit, a preset value storing circuit, and a current supplying circuit. The temperature detecting circuit is configured to generate a first temperature voltage in accordance with an ambient temperature and a current. The preset value storing circuit stores a second temperature voltage preset for a predetermined ambient temperature as a digital value. The current supplying circuit supplies the current to the temperature detecting circuit. The current supplying circuit supplies the current such that the first temperature voltage generated by the temperature detecting circuit at the predetermined ambient temperature is equal to the second temperature voltage. d sidewall, said base, sidewall and cover defining a closed space in said package; (b) a first semiconductor chip mounted in a recess in said base adjacent to said closed space; and (d) a second semiconductor chip mounted on said cover; wherein said closed space is configured to prevent transfer of substantially all heat generated by the second semiconductor chip to the first semiconductor chip. 3. The semiconductor device as set forth in claim 2, wherein each of said base and said cover is comprised of a printed wiring board. 4. The semiconductor device as set forth in claim 2, wherein said cover is comprised of a metal plate. 5. The semiconductor device as set forth in claim 2, wherein said base is formed therein with a first wiring terminal appearing at an upper surface of said base, and said sidewall is formed therein with a second wiring terminal appearing at a lower surface of said sidewall, said semiconductor device further comprising a solder ball located between said base and said sidewall, said first and second wiring terminals being electrically connected to each other through said solder ball. 6. The semiconductor device as set forth in claim 2, wherein said sidewall is formed therein with a wiring terminal appearing at an upper surface of said sidewall, said semiconductor device further comprising a bonding wire through which said second semiconductor chip is electrically connected to said wiring terminal. 7. The semiconductor device as set forth in claim 2, wherein said base is formed therein with a wiring terminal appearing at an upper surface of said base, said semiconductor device further comprising a bonding wire through which said first semiconductor chip is electrically connected to said wiring terminal. 8. The semiconductor device of claim 2, wherein said cover is substantially made from an electrically conductive material. 9. The semiconductor device of claim 8, wherein the material is a metal. 10. A semiconductor device comprising: (a) a plurality of packages vertically stacked on one another, each of said packages being comprised of a base, a sidewall standing on said base at a periphery of said base, and a cover mounted over said sidewall, said base, sidewall and cover defining a closed space in each of said packages; and (b) a plurality of semiconductor chips each mounted in the recess in the base of one of said packaged adjacent to the closed space defined in the package; wherein each closed space is configured to prevent transfer of substantially all heat generated by ones of the plurality of semiconductor chips outside of the closed space to the semiconductor chip arranged in the closed space. 11. The semiconductor device as set forth in claim 10, wherein each of said base and said cover is comprised of a printed wiring board. 12. The semiconductor device as set forth in claim 10, wherein said cover is comprised of a metal plate. 13. The semiconductor device as set forth in claim 10, wherein said base is formed therein with a first wiring terminal appearing at an upper surface of said base, and said sidewall is formed therein with a second wiring terminal appearing at a lower surface of said sidewall, said semiconductor device further comprising solder balls each located between said base and said sidewall, said first and second wiring terminals being electrically connected to each other through each of said solder balls. 14. The semiconductor device as set forth in claim 10, wherein said sidewall is formed therein with a wiring terminal appearing at an upper surface of said sidewall, said semiconductor device further comprising bonding wires through each of which a semiconductor chip mounted on a package which said sidewall partially constitutes is electrically connected to said wiring terminal. 15. The semiconductor device as set forth in claim 10, wherein said base is formed therein with a wiring terminal appearing at an upper surface of said base, said se