초록 ▼

An integrated circuit having a serial data input pin and a serial data output pin, on-chip functional circuitry comprising at least two processing cores, a data adaptor which is in communication with the processing cores by respective communication channels and is connectable to the input and output

An integrated circuit having a serial data input pin and a serial data output pin, on-chip functional circuitry comprising at least two processing cores, a data adaptor which is in communication with the processing cores by respective communication channels and is connectable to the input and output pins. The data adaptor includes transmit circuitry, including circuitry for receiving parallel data and control signals from on-chip functional circuitry and circuitry for converting parallel data and control signals into a sequence of serial bits including flow control bits, data bits and channel identification bits that identify the communication channel on which parallel data and control signals were received. The adaptor further includes receive circuitry having circuitry for receiving from off-chip via the serial data input pin a sequence of serial bits including flow control bits, data bits and channel identification bits, circuitry for converting the bit sequence into parallel data and control signals for the on-chip functional circuitry and circuitry for transmitting parallel data and control signals on the communication channel identified by said channel identification bits.

대표청구항 ▼

An integrated circuit having a serial data input pin and a serial data output pin, on-chip functional circuitry comprising at least two processing cores, a data adaptor which is in communication with the processing cores by respective communication channels and is connectable to the input and output

An integrated circuit having a serial data input pin and a serial data output pin, on-chip functional circuitry comprising at least two processing cores, a data adaptor which is in communication with the processing cores by respective communication channels and is connectable to the input and output pins. The data adaptor includes transmit circuitry, including circuitry for receiving parallel data and control signals from on-chip functional circuitry and circuitry for converting parallel data and control signals into a sequence of serial bits including flow control bits, data bits and channel identification bits that identify the communication channel on which parallel data and control signals were received. The adaptor further includes receive circuitry having circuitry for receiving from off-chip via the serial data input pin a sequence of serial bits including flow control bits, data bits and channel identification bits, circuitry for converting the bit sequence into parallel data and control signals for the on-chip functional circuitry and circuitry for transmitting parallel data and control signals on the communication channel identified by said channel identification bits. new data page; (iv) writing the new data from the buffer to the data portion of said new data page, leaving the spare part of said new data page empty; and (v) entering the physical address of said new data page in the spare portion of a last data page of said chain of data pages associated with said physical address. 2. The distributed mapping scheme of claim 1, with additional steps of reading retrievable data of said data page from said mass storage system by identifying said page of said mass storage system having an empty spare part, said additional steps comprising the steps of: providing the physical address at said page of said mass storage system; and locating, for said physical address, a data page that has no entry in the spare part of a data page by searching through the chain of data pages associated with said physical address, identifying the page that has not been updated, said page comprising said retrievable data of the physical address of said page of said mass storage system. 3. A method of implementing a distributed mapping scheme for addressing a mass storage system, comprising the steps of: (a) providing a host software function, said host software function providing a mapping table, said mapping table being controlled by said host software function; initiating said mapping table, creating logical addresses of said mass storage system, said logical addresses providing a one-to-one correspondence between said logical addresses and physical addresses of one data page of said mass storage system, said one data page comprising a data part and a spare part, one physical address pointing to a data page of said mass storage system, spare portions of said data page not being empty pointing to a next data page belonging to a chain of data pages associated with said physical address, a first data page of said chain of data pages comprising an empty spare portion being a data page containing usable data; (b) performing a data update operation of said data part of a data page, comprising the steps of: (i) storing a physical address of said data page; (ii) identifying the logical address corresponding with said physical address of said data page; (iii) copying the data part of said data page to a buffer; (iv) updating the data in the buffer with new data; (iv) locating a new data page of said mass storage system to place the data from the updated buffer, providing a physical address being associated with said new data page; (iv) writing the new data from-the buffer to the data portion of said new data page, leaving the spare part of said new data page empty; and (v) entering the physical address of said new data page in the spare portion of a last data page of said chain of data pages associated with said physical address. 4. The method of claim 3, with additional steps of reading retrievable data of said data page from said mass storage system by identifying said page of said mass storage system having an empty spare part, said additional steps comprising the steps of: providing the physical address at said page of said mass storage system; and locating, for said physical address, a data page that has no entry in the spare part of a data page by searching through the chain of data pages associated with said physical address, identifying the page that has not been updated, said page comprising said retrievable data of the physical address of said page of said mass storage system. 5. A flash memory for use as a mass storage system, comprising the functions of: (a) providing a host software function, said host software function providing a mapping table,: said mapping table being controlled by said host software function; initiating said mapping table, creating logical addresses of said mass storage system, said logical addresses providing a one-to-one correspondence between said logical addresses and physical addresses of one data page of said mass storage system, said one data page comprising a data segment and a spare segment, one physical address pointing to a data page of said mass storage system, spare portions of said data page not being empty pointing to a next data page belonging to a chain of data pages associated with said physical address, a first data page of said chain of data pages comprising an empty spare portion being a data page containing usable data; (b) performing a data update operation of said data segment of a data page, comprising the steps of: (i) storing a physical address of said data page; (ii) identifying the logical address corresponding with said physical address of said data page; (iii) copying the data segment of said data page to a buffer; (iv) updating the data in the buffer with new data; (iv) locating a new data page of said mass storage system to place the data from the updated buffer, providing a physical address being associated with said new data page; (iv) writing the new data from the buffer to the data portion of said new data page, leaving the spare segment of said new data page empty; and (v) entering the physical address of said new data page in the spare portion of a last data page of said chain of data pages associated with said physical address. 6. A flash memory of claim 5, with additional functions of reading retrievable data of said data page from said mass storage system by identifying said page of said mass storage system having an empty spare segment, said additional functions comprising the steps of: providing the physical address at said page of said mass storage system; locating, for said physical address, a data page that has no entry in the spare segment of a data page by searching through the chain of data pages associated with said physical address, identifying the page that has not been updated, said page comprising said retrievable data of the physical address of said page of said mass storage system. 7. A flash memory for the use as a mass storage system, comprising: (1) a plurality of blocks for storing data in said flask memory; (2) each of said blocks comprising a plurality of pages; each of said pages comprising a header segment and a data segment; and (3) wherein an address mapping table for said flash memory is distributed among said header segments, said address mapping table being supported by a data update operation of said data segment of a data page, said address mapping table comprising: (i) data pages being addressed by physical addresses; (ii) said data pages comprising a data segment and a spare segment; (iii) being controlled by a host software function; (iv) having been initiated, having created logical addresses of said mass storage system; (v) said logical addresses providing a one-to-one correspondence between said logical addresses and physical addresses of said mass storage system; (vi) one physical address pointing to a data page of said mass storage system; (vii) spare portions of said data page not being empty pointing to a next data page belonging to a chain of data pages associated with said physical address; and (viii) a first data page of said chain of data pages comprising an empty spare portion being a data page containing usable data. 8. The flash memory of claim 7, said data update operation of said data segment of a data page comprising the steps of: storing a physical address of said data page; identifying the logical address corresponding with said physical address of said data page; copying the data segment of said data page to a buffer; updating the data in the buffer with new data; locating a new data page of said mass storage system to place the data from the updated buffer, providing a physical address being associated with said new data page; writing the new data from the buffer to the data portion of said new data page, leaving the spare segment at said new data page empty; and entering the physical address of said new data page in the spare portio n of a last data page of said chain of data pages associated with said physical address. 9. The flash memory of claim 7, with additional functions of reading retrievable data of said data page from said mass storage system by identifying said page of said mass storage system having an empty spare segment, said additional functions comprising the steps of: providing the physical address at said page of said mass storage system; and locating, for said physical address, a data page that has no entry in the spare segment of a data page by searching through the chain of data pages associated with said physical address, identifying the page that has not been updated, said page comprising said retrievable data of the physical address of said page of said mass storage system.