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Intermediate-grain reconfigurable processing device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/177
출원번호 US-0293887 (2002-11-12)
발명자 / 주소
  • DeHon, Andre
  • Mirsky, Ethan
  • Knight, Jr., Thomas F.
출원인 / 주소
  • Massachusetts Institute of Technology
대리인 / 주소
    Hamilton, Brook, Smith & Reynolds, P.C.
인용정보 피인용 횟수 : 6  인용 특허 : 30

초록

A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources, such as memory and processing, are deployable in a way that takes advantage of the opportunities for op

대표청구항

1. A programmable integrated circuit comprising: a plurality of like functional units arranged to perform operations on data in response to instructions and to store configuration data, each functional unit including a first memory and an arithmetic and logic unit; a plurality of second memories

이 특허에 인용된 특허 (30)

  1. Deering Michael F. (Mountain View CA), Arithmetic logic system using the output of a first alu to control the operation of a second alu.
  2. Morton Steven G. (Oxford CT), Array reconfiguration apparatus and methods particularly adapted for use with very large scale integrated circuits.
  3. Duval James R. (Shrewsbury MA) Hunt Thomas E. (Brookline NH) Peterson Kevin R. (Stow MA), Configurable data path arrangement for resolving data type incompatibility.
  4. Freeman Ross H. (San Jose CA), Configurable electrical circuit having configurable logic elements and configurable interconnects.
  5. Popli Sanjay (Sunnyvale CA) Pickett Scott (Los Gatos CA) Hawley David (Belmont CA) Moni Shankar (Santa Clara CA) Camarota Rafael C. (San Jose CA), Configuration features in a configurable logic array.
  6. Ing-Simmons Nicholas K. (Oakley TX GB2) Guttag Karl M. (Missouri City TX) Gove Robert J. (Plano TX) Balmer Keith (Bedford GB2), Dual mode SIMD/MIMD processor providing reuse of MIMD instruction memories as data memories when operating in SIMD mode.
  7. Casselman Steven Mark (Reseda CA), FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in.
  8. McCollum John L. (Saratoga CA), Field programmable digital signal processing array integrated circuit.
  9. Cook Peter W. (Mount Kisco NY), IC chips including ALUs and identical register files whereby a number of ALUs directly and concurrently write results to.
  10. Shams Soheil ; Shu David B., Independently non-homogeneously dynamically reconfigurable two dimensional interprocessor communication topology for SIMD multi-processors and apparatus for implementing same.
  11. DeHon Andre ; Mirsky Ethan ; Knight ; Jr. Thomas F., Intermediate-grain reconfigurable processing device.
  12. Wade Jon P. ; Cassiday Daniel R. ; Lordi Robert D. ; Steele ; Jr. Guy Lewis ; St. Pierre Margaret A. ; Wong-Chan Monica C. ; Abuhamdeh Zahi S. ; Douglas David C. ; Ganmukhi Mahesh N. ; Hill Jeffrey V, Massively parallel computer including auxiliary vector processor.
  13. Grondalski Robert S. (Maynard MA), Mechanism for broadcasting data in a massively parallell array processing system.
  14. Chen Steve S. (Eau Claire WI) Beard Douglas R. (Eleva WI) Spix George A. (Eau Claire WI) Priest Edward C. (Eau Claire WI) Wastlick John M. (Eau Claire WI) VanDyke James M. (Eau Claire WI), Method and apparatus for a unified parallel processing architecture.
  15. Heil Thomas F. (Easley SC) Robbins Daniel C. (Easley SC) McDonald Edward A. (Lexington SC), Method and apparatus for decoding bus master arbitration levels to optimize memory transfers.
  16. Guyer James M. (Marlboro MA) Epstein David I. (Framingham MA) Keating David L. (Holliston MA) Anderson Walker (Arlington MA) Veres James E. (Framingham MA) Kimmens Harold R. (Hudson MA), Method and apparatus for enhancing the operation of a data processing system.
  17. Gove Robert J. (Plano TX) Balmer Keith (Bedford GB2) Ing-Simmons Nicholas K. (Bedford TX GB2) Guttag Karl M. (Missouri City TX), Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD).
  18. Thepaut Andr (Plouzane FRX) Ouvradou Gerald (Plouzane FRX), Multiprocessor system with cascaded modules combining processors through a programmable logic cell array.
  19. Zak Robert C. (Lexington MA) Leiserson Charles E. (Winchester MA) Kuzmaul Bradley C. (Waltham MA) Yang Shaw-Wen (Waltham MA) Hillis W. Daniel (Cambridge MA) Douglas David C. (Concord MA) Potter David, Parallel computer system including arrangement for transferring messages from a source processor to selected ones of a p.
  20. Gifford David K. (Cambridge MA), Parallel processing system with processor array having memory system included in system memory.
  21. Chiarulli Donald M. (4724 Newcomb Dr. Baton Rouge LA 70808) Rudd W. G. (Dept. of Computer Science Oregon State University Corvallis OR 97331) Buell Duncan A. (1212 Chippenham Dr. Baton Rouge LA 70808, Processor utilizing reconfigurable process segments to accomodate data word length.
  22. Agrawal Om P. (San Jose CA) Wright Michael J. (Menlo Park CA) Shen Ju (San Jose CA), Programmable gate array with improved interconnect structure, input/output structure and configurable logic block.
  23. Ong Randy T. (Cupertino CA), Programmable logic device which stores more than one configuration and means for switching configurations.
  24. Pombo Raul (Plantation FL) Borras Jaime (Hialeah FL) Bron Michel (Lausanne CHX), Protection circuit for a microprocessor.
  25. Gove Robert J. (Plano TX) Balmer Keith (Bedford GB2) Ing-Simmons Nicholas K. (Bedford GB2) Guttag Karl M. (Missouri City TX), Reconfigurable SIMD/MIMD processor using switch matrix to allow access to a parameter memory by any of the plurality of.
  26. Saccardi Raymond J. (Laurel MD), Reconfigurable pipelined processor.
  27. Gorin Allen L. (Fair Lawn NJ) Makofsky Patrick A. (Randolph NJ) Morton Nancy (Dover NJ) Oliver Neal C. (Madison NJ) Shively Richard R. (Convent Station NJ) Stanziola Christopher A. (Hyde Park NY), Reconfigurable signal processor.
  28. Shindo Tatsuya,JPX ; Kawamura Kaoru,JPX ; Umeda Masanobu,JPX ; Shibuya Toshiyuki ; Miwatari Hideki,JPX, SIMD system having logic units arranged in stages of tree structure and operation of stages controlled through respective control registers.
  29. Gephardt Douglas D. ; Stewart Brett B. ; Wisor Rita M. ; Belt Steven L. ; Dutton Drew J., System for dynamically reconfiguring subbusses of data bus according to system needs based on monitoring each of the inf.
  30. Papadopoulos Gregory M. (Arlington MA) Culler David E. (Boston MA) Arvind (Arlington MA), Tagged token data processing system with operand matching in activation frames.

이 특허를 인용한 특허 (6)

  1. Sutou, Shin-ichi, Dynamic reconfigurable circuit with a plurality of processing elements, data network, configuration memory, and immediate value network.
  2. Watt,William; Verheyen,Henry T., Hardware acceleration system for logic simulation using shift register as local cache.
  3. Ray,Nicholas John Charles; Olgiati,Andrea; Stansfield,Anthony I.; Marshall,Alan D, Loosely-biased heterogeneous reconfigurable arrays.
  4. Kanstein, Andreas; Berekovic, Mladen, Reconfigurable multi-processing coarse-grain array.
  5. Ramesh, Tirumale K., Scalable FPGA fabric architecture with protocol converting bus interface and reconfigurable communication path to SIMD processing elements.
  6. Ramesh,Tirumale K., Super-reconfigurable fabric architecture (SURFA): a multi-FPGA parallel processing architecture for COTS hybrid computing framework.
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