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Image sensor semiconductor package with castellation 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/02
  • H01L-023/12
  • H01L-023/10
  • H01L-023/28
출원번호 US-0128276 (2002-04-24)
발명자 / 주소
  • Chen, James
  • Wang, Rong-Huei
출원인 / 주소
  • Scientek Corp.
대리인 / 주소
    Rosenberg, Klein & Lee
인용정보 피인용 횟수 : 59  인용 특허 : 9

초록

A non-ceramic image sensor semiconductor package with improved moisture resistance, lower cost, and higher reliability is provided. A semiconductor chip with a vision chip active area is attached to a multi-layer resin mask organic substrate. A plurality of bonding wires are attached between parts o

대표청구항

A non-ceramic image sensor semiconductor package with improved moisture resistance, lower cost, and higher reliability is provided. A semiconductor chip with a vision chip active area is attached to a multi-layer resin mask organic substrate. A plurality of bonding wires are attached between parts o

이 특허에 인용된 특허 (9)

  1. Kusaka Teruo,JPX, EL display device using organic EL element having a printed circuit board.
  2. Hashemi Hassan S., Leadless chip carrier design and structure.
  3. Nomi Victor K. ; Pastore John R. ; Reeves Twila J., Method for plating using nested plating buses and semiconductor device having the same.
  4. Glenn Thomas P., Method of making an integrated circuit package employing a transparent encapsulant.
  5. Glenn Thomas P., Plastic package for an optical integrated circuit device and method of making.
  6. Ootake Kenichi,JPX, Resin sealing structure for elements.
  7. Akihiro Murata JP, Semiconductor apparatus substrate, semiconductor apparatus, and method of manufacturing thereof and electronic apparatus.
  8. Yukinobu Wataya JP; Hideto Isono JP, Semiconductor device including solid state imaging device.
  9. Kitaoka Kouki (Sakurai JPX) Maeda Takamichi (Ikoma JPX) Minamide Shozo (Naga-ken JPX), Solid state imaging device having a solid state image sensor and its peripheral IC mounted on one package.

이 특허를 인용한 특허 (59)

  1. Mostafazadeh,Shahram; Smith,Joseph O., Apparatus and method for force mounting semiconductor packages to printed circuit boards.
  2. Sirinorakul, Saravuth, Apparatus for and methods of attaching heat slugs to package tops.
  3. Sirinorakul, Saravuth, Auxiliary leadframe member for stabilizing the bond wire process.
  4. Sirinorakul, Saravuth, Auxiliary leadframe member for stabilizing the bond wire process.
  5. Sirinorakul, Saravuth; Nondhasitthichai, Somchai, Flip chip cavity package.
  6. Sirinorakul, Saravuth; Nondhasitthichai, Somchai, Flip chip cavity package.
  7. Tam, Samuel Waising; Pang, Tak Shing, Imager module with castellated interposer chip.
  8. Chi, HeeJo; Cho, NamJu; Shin, HanGil, Integrated circuit packaging system with stiffener and method of manufacture thereof.
  9. Nondhasitthichai, Somchai; Sirinorakul, Saravuth; Kongthaworn, Kasemsan; Suwannaset, Vorajit, Lead frame ball grid array with traces under die.
  10. Nondhasitthichai, Somchai; Sirinorakul, Saravuth; Kongthaworn, Kasemsan; Suwannaset, Vorajit, Lead frame ball grid array with traces under die.
  11. Sirinorakul, Saravuth, Lead frame ball grid array with traces under die having interlocking features.
  12. Sirinorakul, Saravuth, Lead frame ball grid array with traces under die having interlocking features.
  13. Nondhasittichai, Somchai; Sirinorakul, Saravuth, Lead frame land grid array.
  14. Nondhasitthichai, Somchai; Sirinorakul, Saravuth; Kongthaworn, Kasemsan; Suwannaset, Vorajit, Lead frame land grid array with routing connector trace under unit.
  15. Nondhasitthichai, Somchai; Sirinorakul, Saravuth; Kongthaworn, Kasemsan; Suwannaset, Vorajit, Lead frame land grid array with routing connector trace under unit.
  16. Sirinorakul, Saravuth, Leadframe based multi terminal IC package.
  17. Sirinorakul, Saravuth, Leadframe based multi terminal IC package.
  18. Sirinorakul, Saravuth; Yenrudee, Suebphong, Leadframe feature to minimize flip-chip semiconductor die collapse during flip-chip reflow.
  19. Tsai, Chung-Che, Light sensitive semiconductor package and fabrication method thereof.
  20. Benjavasukul, Woraya; Somrubpornpinan, Thipyaporn; Charapaka, Panikan, Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide.
  21. Benjavasukul, Woraya; Somrubpornpinan, Thipyaporn; Charapaka, Panikan, Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide.
  22. Benjavasukul, Woraya; Somrubpornpinan, Thipyaporn; Charapaka, Panikan, Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide.
  23. Sirinorakul, Saravuth; Nondhasitthichai, Somchai, Method and apparatus for no lead semiconductor package.
  24. Nondhasitthichai, Somchai; Sirinorakul, Saravuth, Method for forming lead frame land grid array.
  25. Sirinorakul, Saravuth; Yenrudee, Suebphong, Methods of manufacturing semiconductor devices including terminals with internal routing interconnections.
  26. Nondhasitthichai, Somchai; Sirinorakul, Saravuth, Molded leadframe substrate semiconductor package.
  27. Nondhasitthichai, Somchai; Sirinorakul, Saravuth, Molded leadframe substrate semiconductor package.
  28. Nondhasitthichai, Somchai; Sirinorakul, Saravuth, Molded leadframe substrate semiconductor package.
  29. Nondhasitthichai, Somchai; Sirinorakul, Saravuth, Molded leadframe substrate semiconductor package.
  30. Nondhasitthichai, Somchai; Sirinorakul, Saravuth, Molded leadframe substrate semiconductor package.
  31. Nondhasitthichai, Somchai; Sirinorakul, Saravuth, Molded leadframe substrate semiconductor package.
  32. Sirinorakul, Saravuth; Nondhasitthichai, Somchai, Molded leadframe substrate semiconductor package.
  33. Minamio,Masanori, Optical device and method for fabricating the same.
  34. Exposito, Juan; Brechignac, Remi, Optical semiconductor housing and method for making same.
  35. Takayama, Yoshiki, Package for an optical device.
  36. Ono, Koji, Package manufacturing method and semiconductor device.
  37. Sirinorakul, Saravuth; Nondhasitthichai, Somchai, Package with heat transfer.
  38. Sirinorakul, Saravuth; Nondhasitthichai, Somchai, Package with heat transfer.
  39. Sirinorakul, Saravuth, Plated terminals with routing interconnections semiconductor device.
  40. Sirinorakul, Saravuth, Plated terminals with routing interconnections semiconductor device.
  41. Sirinorakul, Saravuth, Plated terminals with routing interconnections semiconductor device.
  42. Sirinorakul, Saravuth, Plated terminals with routing interconnections semiconductor device.
  43. Sirinorakul, Saravuth, Post-mold for semiconductor package having exposed traces.
  44. Sirinorakul, Saravuth, Post-mold for semiconductor package having exposed traces.
  45. Sirinorakul, Saravuth; Yenrudee, Suebphong, Protruding terminals with internal routing interconnections semiconductor device.
  46. Chung, Kam Cheong; Zulmuhtasyim, Ahmad; Cheng, Liang Peng; Chan, Lai Theng, Semiconductor device package and method of manufacturing the same.
  47. Sirinorakul, Saravuth, Semiconductor package with full plating on contact side surfaces and methods thereof.
  48. Sirinorakul, Saravuth; Yenrudee, Suebphong, Semiconductor package with multiple molding routing layers and a method of manufacturing the same.
  49. Sirinorakul, Saravuth; Yenrudee, Suebphong, Semiconductor package with multiple molding routing layers and a method of manufacturing the same.
  50. Sirinorakul, Saravuth; Yenrudee, Suebphong, Semiconductor package with multiple molding routing layers and a method of manufacturing the same.
  51. Sirinorakul, Saravuth; Yenrudee, Suebphong, Semiconductor package with multiple molding routing layers and a method of manufacturing the same.
  52. Sirinorakul, Saravuth; Yenrudee, Suebphong, Semiconductor package with multiple molding routing layers and a method of manufacturing the same.
  53. Sirinorakul, Saravuth; Yenrudee, Suebphong, Semiconductor package with multiple molding routing layers and a method of manufacturing the same.
  54. Yenrudee, Suebphong; Kongpoung, Chanapat; Hongsongkiat, Sant; Ounkaew, Siriwanna; Injan, Chatchawan; Sirinorakul, Saravuth, Semiconductor package with plated metal shielding and a method thereof.
  55. Tsuji, Koji; Sanagawa, Yoshiharu; Kirihara, Masao; Gouda, Kazuo; Nishijima, Youichi, Sensor device, sensor system and methods for manufacturing them.
  56. Farnworth, Warren M.; Wood, Alan G.; Wark, James M.; Hembree, David R.; Lake, Rickie C., Spacers for packaged microelectronic imagers and methods of making and using spacers for wafer-level packaging of imagers.
  57. Ohno, Yasuo; Ota, Chiharu, Spread illuminating apparatus.
  58. Nondhasitthichai, Somchai; Sirinorakul, Saravuth, Very extremely thin semiconductor package.
  59. Nondhasitthichai, Somchai; Sirinorakul, Saravuth, Very extremely thin semiconductor package.
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