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A system of pitch attitude symbols, which can be generated by a head-up display unit of an air vehicle, is provided. The system of pitch attitude symbols can be displayed by the head-up display as a virtual image in the direction of flight, behind the cockpit screen in a focal plane in front of the

A system of pitch attitude symbols, which can be generated by a head-up display unit of an air vehicle, is provided. The system of pitch attitude symbols can be displayed by the head-up display as a virtual image in the direction of flight, behind the cockpit screen in a focal plane in front of the background. An unequivocal system of pitch attitude symbols is provided for the pilot, for a display area of an HUD, which display area is arranged below the natural horizon during neutral flight attitude of an air vehicle. Within the focal plane, the system of pitch attitude symbols comprises at least one pitch attitude representation area, arranged in perspective, which pitch attitude representation area can always be arranged parallel to the surface of the earth. The rear edge of the pitch attitude representation area is tiltably fixed in a rear edge axis and, depending on the pitch attitude of the air vehicle, the pitch attitude representation area can be tilted on the focal plane. The front edge shows the pitch attitude in relation to an angular-degree scale.

대표청구항 ▼

A system of pitch attitude symbols, which can be generated by a head-up display unit of an air vehicle, is provided. The system of pitch attitude symbols can be displayed by the head-up display as a virtual image in the direction of flight, behind the cockpit screen in a focal plane in front of the

A system of pitch attitude symbols, which can be generated by a head-up display unit of an air vehicle, is provided. The system of pitch attitude symbols can be displayed by the head-up display as a virtual image in the direction of flight, behind the cockpit screen in a focal plane in front of the background. An unequivocal system of pitch attitude symbols is provided for the pilot, for a display area of an HUD, which display area is arranged below the natural horizon during neutral flight attitude of an air vehicle. Within the focal plane, the system of pitch attitude symbols comprises at least one pitch attitude representation area, arranged in perspective, which pitch attitude representation area can always be arranged parallel to the surface of the earth. The rear edge of the pitch attitude representation area is tiltably fixed in a rear edge axis and, depending on the pitch attitude of the air vehicle, the pitch attitude representation area can be tilted on the focal plane. The front edge shows the pitch attitude in relation to an angular-degree scale. n parallel with the anti-fuse, and having a drain coupled to the first power supply, a source coupled to the intermediate node, and a gate electrode coupled to respond to a program signal to program the anti-fuse; and a second transistor arranged in series with the anti-fuse and the first transistor, and having a drain coupled to the intermediate node, a source coupled to a second power supply, and a gate electrode coupled to respond to the program signal to sustain a voltage needed to program the anti-fuse. 2. An anti-fuse structure as claimed in claim 1, wherein the first power supply is the voltage needed to program the anti-fuse, the second power supply is ground, the first transistor is a vertical-source-drain NMOS transistor operable to tolerate high voltage at both source and drain side, and the second transistor is a vertical-drain NMOS transistor operable to tolerate high voltage at the drain side. 3. An anti-fuse structure as claimed in claim 1, wherein the anti-fuse is a PMOS gate oxide capacitor comprised of an oxide layer exhibiting a high impedance before being programmed, and a low impedance after being programmed. 4. An anti-fuse structure as claimed in claim 1, wherein the anti-fuse is formed in a N-well of a P-substrate, the anti-fuse comprising: source/drain regions formed and spaced-apart in the N-well, and heavily doped with P+ dopant(s); a diffusion region formed in the N-well, and heavily doped with N+ dopant(s); shallow trench isolation (STI) regions formed in the N-well to provide isolation between the diffusion region and the source/drain regions; a gate electrode formed over the source and drain regions, and isolated from the source and drain regions by an oxide layer; metal lines bonded to the source/drain regions and the diffusion region, for coupling the source/drain regions to the first power voltage; and an insulation layer deposited on the P-substrate including the N-well. 5. An anti-fuse structure as claimed in claim 1, further comprising: a second anti-fuse operable in a normal "open" state and a programmed "shorted" state, and having a first electrode coupled to the first power supply, and a second electrode coupled to a second intermediate node; a third transistor arranged in parallel with the second anti-fuse, and having a drain coupled to the first power supply, a source coupled to the second intermediate node, and a gate electrode coupled to respond to a second program signal to protect the second anti-fuse from stress during programming; and a fourth transistor arranged in series with the second anti-fuse and the third transistor, and having a drain coupled to the second intermediate node, a source coupled to the second power supply, and a gate electrode coupled to respond the second program signal to sustain a voltage needed to program the second anti-fuse. 6. An anti-fuse structure as claimed in claim 5, wherein the first power supply is the voltage needed to program the anti-fuse, the second power supply is ground, the first and third transistors are vertical-source-drain NMOS transistors operable to tolerate high voltage at both source and drain side, and the second and fourth transistors are vertical-drain NMOS transistors operable to tolerate high voltage at the drain side. 7. An anti-fuse structure as claimed in claim 6, wherein the first and second anti-fuses are PMOS gate oxide capacitors each of which is comprised of an oxide layer s exhibiting a high impedance before being programmed, and a low impedance after being programmed. 8. An anti-fuse structure as claimed in claim 1, further comprising an anti-fuse program circuit arranged to program the anti-fuse through application of the program signal to the first and second transistors, the anti-fuse program circuit comprising: a logic gate disposed between a core voltage node and a ground node, and arranged to receive the program signal and a sense signal, and activate an active "low" state at an output t