IPC분류정보
| 국가/구분 |
United States(US) Patent
등록
|
| 국제특허분류(IPC7판) |
|
| 출원번호 |
US-0610929
(2000-07-06)
|
|
발명자
/ 주소 |
- Jayaramen, Sudaresan
- Park, Sungmee
- Rajamanickam, Rangaswamy
- Gopalsamy, Chandramohan
|
| 출원인 / 주소 |
- Georgia Tech Research Corp.
|
| 대리인 / 주소 |
Thomas, Kayden, Horstemeyer & Risley LLP
|
| 인용정보 |
피인용 횟수 :
92 인용 특허 :
66 |
초록
▼
A garment for infants comprises a comfort component serving as a base, a plurality of signal transmission paths integrated within the comfort component; and at least one interface that provides a transmission path between the information infrastructure component and an external device. In addition,
A garment for infants comprises a comfort component serving as a base, a plurality of signal transmission paths integrated within the comfort component; and at least one interface that provides a transmission path between the information infrastructure component and an external device. In addition, the garment has the means to ensure a snug fit for the baby so that the sensors stay in place to minimize the risk of false alarms while the baby is safe and comfortable. This feature also helps to extend the usable life of the garment as the baby grows.
대표청구항
▼
A garment for infants comprises a comfort component serving as a base, a plurality of signal transmission paths integrated within the comfort component; and at least one interface that provides a transmission path between the information infrastructure component and an external device. In addition,
A garment for infants comprises a comfort component serving as a base, a plurality of signal transmission paths integrated within the comfort component; and at least one interface that provides a transmission path between the information infrastructure component and an external device. In addition, the garment has the means to ensure a snug fit for the baby so that the sensors stay in place to minimize the risk of false alarms while the baby is safe and comfortable. This feature also helps to extend the usable life of the garment as the baby grows. orm said sampling using pulses of a control signal, wherein at least a portion of said FET structure conducts during each said pulse of said control signal provided that said first signal is within a voltage range; and (2) storing said transferred energy, wherein said stored energy forms said second signal; wherein said transfer of energy from said first signal substantially prevents accurate voltage reproduction of the first signal during apertures of said control signal. 11. The method of claim 10, wherein said complementary FET structure comprises an n-channel FET and a p-channel FET. 12. The method of claim 11, wherein said n-channel FET and said p-channel FET are electrically coupled to a first node of a capacitor, and a second node of said capacitor is coupled to a voltage reference, and wherein said n-channel FET and said p-channel FET receive said first signal. 13. The method of claim 12, wherein said voltage reference is ground. 14. The method of claim 10, wherein said FET structure is electrically coupled to at least one capacitor, wherein said at least one capacitor receives said first signal comprising one or more input signals. 15. The method of claim 14, wherein said at least one capacitor includes first and second capacitors. 16. A circuit for down-converting a first signal to produce a lower frequency second signal, comprising: a control signal generator that outputs a control signal; a complementary field effect transistor (FET) structure, wherein said FET structure is controlled using said control signal, wherein said FET structure comprises an n-channel FET having a source, gate, and drain, and also comprises a p-channel FET having a source, gate, and drain, wherein said sources of said n-channel and p-channel FETS are electrically coupled to each other, and said drains of said n-channel and p-channel FETS are electrically coupled to each other, and said first signal is electrically coupled to said sources of said p-channel and n-channel FETs; and at least one capacitor electrically coupled to said complementary FET structure: wherein substantial energy is transferred from the input signal to the at least one capacitor. 17. The circuit of claim 16, wherein said gates of said n-channel and p-channel FETS are electrically coupled to said control signal. 18. The circuit of claim 17, further comprising a delay element, wherein said gate of said n-channel FET is coupled to said control signal via said delay element. 19. The circuit of claim 17, further comprising an inverter, wherein said gate of said p-channel FET is coupled to said control signal via said inverter. 20. The circuit of claim 19, wherein said inverter is electrically coupled to a first voltage level and a second voltage level. 21. The circuit of claim 19, wherein said inverter is electrically coupled to a voltage supply. 22. The circuit of claim 16, further comprising: biasing means for biasing said first signal between first and second voltage levels. 23. The circuit of claim 22, wherein said biasing means comprises: first and second voltage supplies electrically coupled to said sources of said n-channel and p-channel FETs. 24. The circuit of claim 23, wherein said first and second voltage supplies are electrically coupled to said sources of said n-channel and p-channel FETs via resistors. 25. The circuit of claim 16, wherein said first signal is electrically coupled to said sources of said p-channel and n-channel FETs via a resistive circuit. 26. The circuit of claim 16, wherein a first node of said at least one capacitor is electrically coupled to said drains of said p-channel and n-channel FETs, and a second node of said at least one capacitor is electrically coupled to a voltage reference. 27. The circuit of claim 26, wherein said voltage reference is ground. 28. The circuit of claim 17, wherein said first signal is electrically coupled to said at least one capacitor. 29. The circuit of claim 28, wherein said first sig
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