초록 ▼

The present invention provides a process for fabricating a metal oxide semiconductor field effect transistor (MOSFET) having a double-gate and a double-channel wherein the gate region is self-aligned to the channel regions and the source/drain diffusion junctions. The present invention also relates

The present invention provides a process for fabricating a metal oxide semiconductor field effect transistor (MOSFET) having a double-gate and a double-channel wherein the gate region is self-aligned to the channel regions and the source/drain diffusion junctions. The present invention also relates to the FIN MOSFFET structure which is formed using method of the present invention.

대표청구항 ▼

1. A method of fabricating a thin vertical channel (FIN) metal oxide semiconductor field effect transistor (MOSFET) comprising the steps of: (a) forming at least one patterned region atop a surface of an insulating region, said at least one patterned region comprising a Si-containing layer presen

1. A method of fabricating a thin vertical channel (FIN) metal oxide semiconductor field effect transistor (MOSFET) comprising the steps of: (a) forming at least one patterned region atop a surface of an insulating region, said at least one patterned region comprising a Si-containing layer present atop said insulating region, a pad oxide present atop said Si-containing layer and a polish stop layer present atop said oxide; (b) forming planarizing insulating region abutting each patterned region, said planarizing insulating region are formed on exposed portions of said insulating region, said planarizing region being co-planar with a top surface of said polish stop layer; (c) forming a hardmask on a portion of said at least one patterned region, said hardmask being used to define vertical channel regions in said at least one patterned region; (d) selectively removing a portion of said hardmask, said polish stop layer and said pad oxide layer so as to expose a portion of said Si-containing layer thereby forming vertical channels regions and a trough having sidewalls; (e) forming insulating spacers on the sidewalls of the trough and forming a gate region between said insulating spacers in said trough, said gate region comprising two regions of gate conductors that are separated from said vertical channel regions by agate dielectric; and (f) removing said polish stop layer and said pad oxide abutting said gate region so as to expose portions of said Si-containing layer and forming source/drain diffusion regions therein thereby providing a double-gated/double channel MOSFET device in which the gate region is self-aligned to the source/drain diffusion regions and vertical channel regions. 2. The method of claim 1 wherein said Si-containing layer and said insulating region are components of a silicon-on-insulating (SOI) material. 3. The method of claim 1 wherein step (a) comprising deposition, lithography and etching. 4. The method of claim 1 wherein said planarizing insulating regions are formed by deposition and planarization. 5. The method of claim 1 wherein said hardmask is formed by deposition of an oxide and patterning. 6. The method of claim 1 wherein step (d) comprising a series of etching processes wherein various etchant gases or plasma are employed to selectively remove desired layers. 7. The method of claim 1 wherein said gate dielectric is formed by deposition or a thermal growing process. 8. The method of claim 1 wherein said gate conductors are formed by deposition and planarization. 9. The method of claim 1 wherein each of said gate conductors is comprised of polysilicon, amorphous silicon, a conductive elemental metal, a nitride or silicide of a conductive elemental metal, an alloy of a conductive elemental metal or multilayers thereof. 10. The method of claim 1 wherein said insulating spacers are formed by deposition and etching. 11. The method of claim 1 wherein said source/drain diffusion regions are formed by ion implantation and activation annealing.