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Systems, methods and protocol for assuring separation of aircraft during parallel approaches. The systems, methods and protocol function in cooperation with existing TCAS to facilitate approaches of multiple aircraft on closely-spaced parallel runways. The systems, methods and protocol utilize data

Systems, methods and protocol for assuring separation of aircraft during parallel approaches. The systems, methods and protocol function in cooperation with existing TCAS to facilitate approaches of multiple aircraft on closely-spaced parallel runways. The systems, methods and protocol utilize data transmissions from equipped aircraft to obtain tracking information which is used in separation algorithms to generate alerts to an observer of possible threats. The systems, methods and protocol facilitate parallel approaches to closely-spaced parallel runways under Instrument Approach Procedure.

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Systems, methods and protocol for assuring separation of aircraft during parallel approaches. The systems, methods and protocol function in cooperation with existing TCAS to facilitate approaches of multiple aircraft on closely-spaced parallel runways. The systems, methods and protocol utilize data

Systems, methods and protocol for assuring separation of aircraft during parallel approaches. The systems, methods and protocol function in cooperation with existing TCAS to facilitate approaches of multiple aircraft on closely-spaced parallel runways. The systems, methods and protocol utilize data transmissions from equipped aircraft to obtain tracking information which is used in separation algorithms to generate alerts to an observer of possible threats. The systems, methods and protocol facilitate parallel approaches to closely-spaced parallel runways under Instrument Approach Procedure. n analysis section for reading test requirements corresponding to one of said numeric codes from said test requirement table; a data circuit for supplying a digital test signal to said D/A converter circuit of said semiconductor integrated circuit to be tested on the basis of said test requirements read by said analysis section; a testing D/A converter circuit which converts the digital test signal from said data circuit into an analog test signal and supplies said analog test signal to said A/D converter circuit of said semiconductor integrated circuit to be tested; a testing A/D converter circuit which converts an analog test output from said D/A converter circuit of said semiconductor integrated circuit to be tested into a digital test output; and measured data memory for storing the digital test output from said A/D converter circuit of said semiconductor integrated circuit to be tested and said digital test output from said testing A/D converter circuit, wherein a result of analysis of said each digital test outputs stored in said measured data memory, the analysis being performed by said analysis section, is sent to said external controller. 2. The apparatus for testing a semiconductor integrated circuit according to claim 1, wherein said external controller is a tester. 3. The apparatus for testing a semiconductor integrated circuit according to claim 1, wherein said memory having stored therein said test requirement table is incorporated in said analysis section. 4. The apparatus for testing a semiconductor integrated circuit according to claim 1, wherein said test ancillary device comprises: a test analysis table having a memory address table for setting an address of the measured data memory in which digital test outputs are stored for a corresponding numeric code; a computation method table having stored therein information about computation methods corresponding to respective numeric codes; and a test specification table in which specification evaluation values corresponding to the respective numeric codes are stored, wherein when an analysis start instruction is received from said external controller along with a numeric code, a predetermined digital test output is read from said memory address table; a corresponding computation method is read from the computation method table, thereby computing a characteristic parameter of said A/D converter circuit of said semiconductor integrated circuit to be tested and a characteristic parameter of said D/A converter circuit of the same; a result of computation is compared with a specification evaluation value corresponding to the numeric code read from said test specification table, thus evaluating a specification; and a result of evaluation is sent to said external controller. 5. The apparatus for testing a semiconductor integrated circuit according to claim 4, wherein said characteristic parameters correspond to a differential linearity and an integral nonlinearity error. 6. The apparatus for testing a semiconductor integrated circuit according to claim 4, wherein transmission information for sending a digital test output is provided in said test analysis table; and, when a numeric code corresponding to transmission information is sent to said test ancillary device from said external controller, said test ancillary device reads a corresponding digital test output from said measured data memory, and the digital test output is sent to said external controller. 7. The apparatus for testing a semiconductor integrated circuit according to claim 6, wherein the numeric code to be used for selecting transmission information is formed by combination of a code representing details of a test and a code to be used for selecting transmission information. 8. A method for testing a semiconductor integrated circuit comprising, a test circuit board configured to transmit signals to and receive signals from a semiconductor integrated circuit to be tested wherein the semic