[미국특허]
Second transfer logic causing a first transfer logic to check a data ready bit prior to each of multibit transfer of a continous transfer operation
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-013/28
G06F-013/42
출원번호
US-0314487
(1999-05-18)
발명자
/ 주소
Ryan, Jr., Lawrence H.
출원인 / 주소
Invensys Systems, Inc.
대리인 / 주소
Powsner, David J.Nutter, McClennen & Fish LLP
인용정보
피인용 횟수 :
15인용 특허 :
175
초록▼
A digital device interface for transferring information between a processor and a control device includes a first serial peripheral interface (SPI), e.g., with "data in," "data out" and "clock" ports, in serial communication with a second SPI. The first SPI can be coupled to, and associated with, th
A digital device interface for transferring information between a processor and a control device includes a first serial peripheral interface (SPI), e.g., with "data in," "data out" and "clock" ports, in serial communication with a second SPI. The first SPI can be coupled to, and associated with, the processor; the second SPI, with the control device. A first transfer logic section, e.g., a shift register engine, transfers bytes, word, longwords or other multi-bit datum between the processor and the control device. A second transfer logic section effects a transfer transaction between the processor and the control device--that is, the transfer of plural multi-bit datum relating to a common data access operation or a common data generation operation. For sensor-type control devices, such a transaction may include, for example, the "continuous" transfer of data sensed by the device. For a servo, actuator, or the like, the transaction may include, for example, a stream of set points or other control data generated by the processor (and/or its related data stores) for application to the control device.
대표청구항▼
A digital device interface for transferring information between a processor and a control device includes a first serial peripheral interface (SPI), e.g., with "data in," "data out" and "clock" ports, in serial communication with a second SPI. The first SPI can be coupled to, and associated with, th
A digital device interface for transferring information between a processor and a control device includes a first serial peripheral interface (SPI), e.g., with "data in," "data out" and "clock" ports, in serial communication with a second SPI. The first SPI can be coupled to, and associated with, the processor; the second SPI, with the control device. A first transfer logic section, e.g., a shift register engine, transfers bytes, word, longwords or other multi-bit datum between the processor and the control device. A second transfer logic section effects a transfer transaction between the processor and the control device--that is, the transfer of plural multi-bit datum relating to a common data access operation or a common data generation operation. For sensor-type control devices, such a transaction may include, for example, the "continuous" transfer of data sensed by the device. For a servo, actuator, or the like, the transaction may include, for example, a stream of set points or other control data generated by the processor (and/or its related data stores) for application to the control device. stem path associated with said withdrawn route to identify its origin Autonomous System. 7. The method according to claim 1 wherein the step of processing said routing data includes the step of detecting the existence of a newly advertised route to independently verify the existence of said newly advertised route. 8. The method according to claim 1 further including the step of measuring loss of packets transmitted between peers. 9. The method according to claim 1 further including the steps of: testing for connectivity between peers; and comparing the connectivity between a first pair of pees to the connectivity between a second pair of peers. 10. A system for detecting and reporting routing violations in a network of interconnected peers comprising: a router for acquiring routing information from each of the peers, including routes advertised by said peers: buffer means for storing said routing information; a monitoring and measurement server for processing the routing information to detect a routing violation and for reporting said violation, where a routing violation is caused routing information. 11. The system according to claim 10 further including a database coupled to the monitoring and measurement server for providing to said server information of officially advertised routes to enable said server to compare the officially advertised routes to those advertised by said peers. 12. The system according to claim 10 further including a trouble ticket system coupled to said server for receiving reports of routing violations, said trouble ticket system, in response to said routing violation, signaling a technician to manually correct said violation. 13. The system according to claim 10 further including a trouble ticket system coupled to said server for receiving reports of routing violations, said trouble ticket system, in response to said routing violation, automatically correcting said violation. 14. The system according to claim 10 further including a trouble ticket system coupled to said server for receiving reports of routing violations, said trouble ticket system, in response to said routing violation, automatically signaling an external system to correct said violation.
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