|국가/구분||United States(US) Patent 등록|
|미국특허분류(USC)||324/760; 324/754; 438/017|
|발명자 / 주소|
|출원인 / 주소|
|대리인 / 주소||
|인용정보||피인용 횟수 : 36 인용 특허 : 4|
A testing apparatus and a fabricating method of a semiconductor integrated circuit device for reducing the fabrication cost by placing, in the wafer level burn-in, divided contactors in equally contact with the full surface of wafer, enabling repair of each contactor and improving the yield of contactors. The cassette structure of the mechanical pressurizing system in the testing apparatus is structured with a plurality of divided silicon contactor blocks and a guide frame for integrating these blocks and employs the wafer full surface simultaneous conta...
1. A semiconductor integrated circuit device fabrication method comprising: performing an electrical test to a plurality of wafer surface regions over a major surface of a wafer, each of said plurality of wafer surface regions including a plurality of chip regions, using a plate holding structure integrally holding a plurality of wiring/stylus composite plates, each of said wiring/stylus composite plates including a first wiring film structure having a plurality of test stylus sections electrically connected thereto, each of the test stylus sections h...