[특허]System and method for predicting and displaying wake vortex turbulence

[미국특허] System and method for predicting and displaying wake vortex turbulence 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G08G-005/04
출원번호	US-0935558 (2001-08-22)
발명자 / 주소	Kuntman, Daryal Brandao, Ruy C. P. Bateman, C. Don
출원인 / 주소	Honeywell International, Inc.
대리인 / 주소	Rupnick, Charles J.
인용정보	피인용 횟수 : 57 인용 특허 : 4

초록

A circuit and method for predicting an intersection of a host aircraft flight path with the wake vortex of another aircraft.

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A circuit and method for predicting an intersection of a host aircraft flight path with the wake vortex of another aircraft. /O block includes a programmable AND array, each programmable AND array being configured to receive the control output signals from its I/O block's routing structure and to provide M product term outputs to its I/O block's I/O cells, and wherein each I/O block's registers may receive data signals from the set of data signals routed by its routing structure. 2. The programmable interconnect circuit of claim 1, wherein the M product term outputs comprise set/reset signals and clock and clock enable signals for controlling the register within each I/O cell. 3. The programmable interconnect circuit of claim 2, wherein each multiplexer for each I/O cell within an I/O block is configured to receive a plurality of signals from its I/O block's routing structure's set of data output signals and select a multiplexer output signal, and wherein each register of each I/O cell within an I/O block comprises an output register coupled to receive the selected signal from its I/O cell's multiplexer and further includes an input register coupled to receive signals from its I/O cell's pin and provide the signals to its I/O cell's routing structure, the M product terms from each I/O block's routing structure further comprising MUX select signals for the I/O block's multiplexers. 4. The programmable interconnect circuit of claim 3, wherein each I/O cell further comprises: an output enable register, wherein each I/O block's M product term signals includes an output enable signal for controlling the I/O block's output enable registers. 5. The programmable interconnect circuit of claim 4, wherein the programmable AND array is further configured to provide the logical OR of signals from the set of M product terms signals used to form the set/reset and clock/clock enable signals. 6. The programmable interconnect circuit of claim 1, further comprising: a non-volatile memory for storing configuration data, wherein the configuration data is used to configure the programmable AND array. 7. The programmable interconnect circuit of claim 6, wherein the non-volatile memory is in-system programmable. 8. The programmable interconnect circuit of claim 1, wherein each routing structure in the plurality of routing structures comprises a data-path routing structure and a control-signal routing structure, each data-path routing structure producing its I/O block's set of data output signals, each control routing structure producing its I/O block's set of control output signals. 9. The programmable interconnect circuit of claim 8, wherein the register in each I/O cell comprises an input register, output register, and an output enable register, the set and reset signals for each input register, output register, and output enable register within an I/O block being derived from the I/O block's set of M product terms. 10. The programmable interconnect circuit of claim 9, wherein clock and clock enable signals for each input register, output register, and output enable register within an I/O block's I/O cells are derived from the I/O block's set of M product terms. 11. The programmable interconnect circuit of claim 10, wherein the same subset of product terms from the set of M product terms are used to derive the clock and clock enable signals for a given I/O cell's output register and output enable register. 12. The programmable interconnect circuit of claim 8, wherein each routing structure programmably routes its control and data signals according to the configuration data stored in the non-volatile memory. 13. The programmable interconnect circuit of claim 12, wherein the non-volatile memory is electrically erasable. 14. A programmable interconnect circuit, comprising; a plurality of input/output (I/O) blocks, each I/O block including a control array and at least two I/O cells, each I/O cell including a multiplexer coupled to an I/O circuit, the control array coupled to the select terminals of each multiplexer and to each I/O circuit; and a routing struc

이 특허에 인용된 특허 (4) 인용/피인용 타임라인 분석

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[미국특허] System and method for predicting and displaying wake vortex turbulence 원문보기

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[미국특허] System and method for predicting and displaying wake vortex turbulence 원문보기

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