초록 ▼

Metrics associated with each branch from a previous hypothesized trellis state to each respective possible current trellis state in a DFSE equalizer can be calculated. In particular, a common portion of branch metrics can be calculated that is common to each of the branch metrics from the previous h

Metrics associated with each branch from a previous hypothesized trellis state to each respective possible current trellis state in a DFSE equalizer can be calculated. In particular, a common portion of branch metrics can be calculated that is common to each of the branch metrics from the previous hypothesized state to each of the current possible states, and difference variables representing a difference between the common portion of the branch metrics and each of the branch metrics from the previous hypothesized state to each of the current possible states can also be calculated. The common portion of the branch metrics and each of the difference variables can then be combined to provide a respective metric for each of the possible current states.

대표청구항 ▼

Metrics associated with each branch from a previous hypothesized trellis state to each respective possible current trellis state in a DFSE equalizer can be calculated. In particular, a common portion of branch metrics can be calculated that is common to each of the branch metrics from the previous h

Metrics associated with each branch from a previous hypothesized trellis state to each respective possible current trellis state in a DFSE equalizer can be calculated. In particular, a common portion of branch metrics can be calculated that is common to each of the branch metrics from the previous hypothesized state to each of the current possible states, and difference variables representing a difference between the common portion of the branch metrics and each of the branch metrics from the previous hypothesized state to each of the current possible states can also be calculated. The common portion of the branch metrics and each of the difference variables can then be combined to provide a respective metric for each of the possible current states. handshake communication between the memory array and an external accessing client. The method and apparatus handles external accesses and refresh operations such that the refresh operations do not interfere with the external accesses under any conditions. As a result, an SRAM compatible device can be built from DRAM or 1-Transistor cells. A clock division scheme is implemented to allow N external accesses and one refresh operation to be performed during N consecutive clock cycles. wherein: the semiconductor memory has a plurality of data output modes in which said read data are output in different orders from one another; and said connection switching circuit includes switching circuits for connecting said sense amplifiers to predetermined ones of said read amplifiers respectively, according to said address and said data output modes. 12. The semiconductor memory according to claim 1, further comprising: a read control circuit for operating only said read amplifier(s) having higher drivability(s) to output data, when a burst length, as a number of times of successively outputting said read data, is set to a singular number. 13. The semiconductor memory according to claim 1, further comprising: a plurality of blocks having said memory cells, said sense amplifiers, said read amplifiers, said data output circuit, and said data bus lines, and corresponding to respective data terminals. 14. The semiconductor memory according to claim 13, wherein: said blocks are arranged in a first direction; and said data bus lines are wired in a second direction orthogonal to said first direction. 15. The semiconductor memory according to claim 14, wherein said first direction is a disposing direction of said data terminals. 16. The semiconductor memory according to claim 14, wherein each of said blocks is divided into a plurality of memory areas in said second direction, and a plurality of said memory areas aligned in said first direction form banks which operate independently. 17. A semiconductor memory comprising: a plurality of memory cells; a plurality of sense amplifiers for amplifying parallel read data from said memory cells, respectively; a plurality of read amplifiers for amplifying said read data amplified in said sense amplifiers up to respective predetermined logic levels, in which at least one of the read amplifiers has a higher drivability than drivabilities of the rest of the read amplifiers; a connection switching circuit for connecting said sense amplifiers to predetermined ones of said read amplifiers, according to an address; a switching circuit being arranged close to said read amplifiers, for outputting said parallel read data amplified in said read amplifiers in sequential order, starting from said read data corresponding to said read amplifier(s) having higher drivability(s), during burst read operation in which said read data are successively outputted; a data output circuit for outputting said read data outputted from said switching circuit; and a data bus line for connecting said switching circuit and said data output circuit. re of a precharge voltage line is provided. The semiconductor memory device includes a plurality of memory cell arrays, a plurality of bit line precharge circuit units, and a first precharge voltage line and a second precharge voltage line. Each of the plurality of memory cell arrays include a plurality of memory cells and a plurality of bit line pairs for outputting and receiving data to and from each of the memory cells and are arranged in a matrix. The plurality of bit line precharge circuit units precharge and equalize corresponding bit line pairs of the memory cell arrays into predetermined precharge voltages. The first precharge voltage line and the second precharge voltage line are arranged in a mesh in each region between the plurality of memory cell arrays. During a first mode of operation, the first precharge voltage line and the second precharge voltage line supply a common precharge voltage and during a second precharge voltage line, precharge voltages having different levels are supplied at the first and the second precharge voltage lines to precharge memory cells adjacent to one another with different precharge voltages. rcuit which stores therein an address of a defect memory cell in the DRAM cell array blocks, a comparison circuit which compares an input address with the address stored in the fuse circuit, and an I/O bus which couple the SRAM redundancy cell to the data buffer in response to an address match found by the comparison circuit. ifying element for selectively modifying the polarization of the beam at said diaphragm, thereby switching between a state in which said portion of the beam is internally reflected and a state in which said portion of the beam is substantially fully transmitted. 14. An optical device according to claim 1, wherein said diaphragm comprises a layer of substantial uniform thickness. 15. An optical device according to claim 1, said device comprising means for scanning an optical record carriers of predetermined different physical formats using scanning and different numerical temperatures provided by said optical diaphragm. 16. An optical diaphragm for use in scanning an optical record carrier using a radiation beam of a predetermined wavelength, said optical diaphragm being for reducing the intensity of a portion of the beam, characterized in that said optical diaphragm includes a cholesteric liquid crystal material having a varying helical pitch selected to provide internal reflection of said portion of the beam. 17. An optical diaphragm according to claim 16, arranged such that when the beam it is in a non-collimated state at said diaphragm, said diaphragm is arranged to provide internal reflection for a selected range of angles of incidence, with which said portion of the beam falls on the optical diaphragm in its non-collimated state. 18. An optical diaphragm according to claim 16, wherein said diaphragm includes only cholesteric material of a special uniform helical pitch. 19. An optical diaphragm according to claim 16, arranged such that when the beam is in a substantially collimated state at said diaphragm, said cholesteric liquid crystal material, having a helical pitch selected to provide internal reflection of said portion of the beam, is selectively located in said portion of said beam. 20. An optical diaphragm according to claim 19, wherein said diaphragm comprises cholesteric liquid crystal material of varying helical pitch, material having a helical pitch within a range providing said internal reflection being selectively located in said diaphragm. 21. An optical diaphragm according to claim 20, wherein said cholesteric liquid crystal material having a helical pitch selected to provide internal reflection of said portion of the beam, comprises an annular ring portion. 22. An optical diaphragm according to claim 21, wherein said diaphragm comprises an inner portion inside said annular ring portion, said inner portion comprising cholesteric material of a different helical pitch than said annular ring portion. 23. An optical diaphragm according to claim 22, wherein said inner portion and said annular ring portion comprise cholesteric having helical pitches selected to match phase changes generated when a selected beam is transmitted through said diaphragm. 24. An optical diaphragm according to claim 16, wherein said diaphragm comprises a cholesteric layer of substantially uniform thickness.