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Method of manufacturing a metal cap layer for preventing damascene conductive lines from oxidation 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/00
출원번호 US-0798101 (2001-03-02)
발명자 / 주소
  • Ning, Xian J.
출원인 / 주소
  • Infineon Technologies AG
대리인 / 주소
    Slater & Matsil, L.L.P.
인용정보 피인용 횟수 : 32  인용 특허 : 8

초록

A semiconductor device (100) having a copper damascene BEOL structure. A metal cap layer (120) is formed over conductive lines (118) to prevent oxidation of the conductive lines (118) during subsequent processing steps. The metal cap layer (120) comprises a material other than the conductive line (1

대표청구항

A semiconductor device (100) having a copper damascene BEOL structure. A metal cap layer (120) is formed over conductive lines (118) to prevent oxidation of the conductive lines (118) during subsequent processing steps. The metal cap layer (120) comprises a material other than the conductive line (1

이 특허에 인용된 특허 (8)

  1. Chen Eugene Y. ; Slaughter Jon M., Magnetic random access memory and fabricating method thereof.
  2. Huang Yuan-Chang,TWX ; Chang Kuan-Hui,TWX, Method of fabricating seamless tungsten plug employing tungsten redeposition and etch back.
  3. Harada Akihiko,JPX ; Saito Takayuki,JPX, Method of manufacturing a semiconductor device.
  4. Gupta Subhash,SGX ; Ho Kwok Keung Paul,SGX ; Zhou Mei-Sheng,SGX ; Chool Simon,SGX, Method to avoid copper contamination on the sidewall of a via or a dual damascene structure.
  5. Zhou Mei Sheng,SGX ; Ho Paul Kwok Keung,SGX ; Gupta Subhash,SGX, Method to create a copper dual damascene structure with less dishing and erosion.
  6. Cote William J. (Poughquag NY) Lee Pei-Ing P. (Williston VT) Sandwick Thomas E. (Hopewell Junction NY) Vollmer Bernd M. (Wappingers Falls NY) Vynorius Victor (Pleasant Valley NY) Wolff Stuart H. (Tul, Refractory metal capped low resistivity metal conductor lines and vias.
  7. Zhao Bin (Austin TX) Vasudev Prahalad K. (Austin TX) Dubin Valery M. (Cupertino CA) Shacham-Diamand Yosef (Ithaca NY) Ting Chiu H. (Saratoga CA), Selective electroless copper deposited interconnect plugs for ULSI applications.
  8. Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.

이 특허를 인용한 특허 (32)

  1. Yates,Donald L.; Drewes,Joel A., Device having improved surface planarity prior to MRAM bit material deposition.
  2. Lee,Hsien Ming; Lin,Jing Cheng; Pan,Shing Chyang; Hsieh,Ching Hua; Peng,Chao Hsien; Huang,Cheng Lin; Su,Li Lin; Shue,Shau Lin, High performance metallization cap layer.
  3. Chae, Moosung; Zhao, Larry, Integrated circuits including selectively deposited metal capping layers on copper lines and methods for fabricating the same.
  4. Yang, Chih Chao; Hsu, Louis L., Interconnect structure with a barrier-redundancy feature.
  5. Yang,Chih Chao; Hsu,Louis L., Interconnect structure with a barrier-redundancy feature.
  6. Nejad,Hasan; Deak,James G., MRAM memory cell having an electroplated bottom layer.
  7. Lee,Gill Yong; O'Sullivan,Eugene, MTJ patterning using free layer wet etching and lift off techniques.
  8. Tuttle,Mark E., Magneto-resistive memory and method of manufacturing the same.
  9. Costrini,Gregory; Findeis,Frank; Lee,Gill Yong; Park,Chanro, Mask schemes for patterning magnetic tunnel junctions.
  10. Sills, Scott E.; Sandhu, Gurtej S.; Tang, Sanh D.; Smythe, John, Memory cell arrays.
  11. Sills, Scott E.; Sandhu, Gurtej S.; Tang, Sanh D.; Smythe, John, Memory cell arrays.
  12. Sills, Scott E.; Ramaswamy, D.V. Nirmal, Memory cell structures.
  13. Ravasio, Marcello; Sciarrillo, Samuele; Gotti, Andrea, Memory cell with independently-sized electrode.
  14. Ravasio, Marcello; Sciarrillo, Samuele; Gotti, Andrea, Memory cell with independently-sized electrode.
  15. Sills, Scott E.; Sandhu, Gurtej S.; Tang, Sanh D.; Smythe, John, Memory cells and memory cell arrays.
  16. Sills, Scott E.; Sandhu, Gurtej S.; Tang, Sanh D.; Smythe, John, Memory cells and memory cell arrays.
  17. Daubenspeck, Timothy H.; Landers, William F.; Zupanski-Nielsen, Donna S., Method for fabricating last level copper-to-C4 connection with interfacial cap structure.
  18. Sciarrillo, Samuele, Methods for forming interconnections between top electrodes in memory cells by a two-step chemical-mechanical polishing (CMP) process.
  19. Noh, Eun-Sun; Park, Jong-Chul; Kwon, Shin; Kwon, Hyung-Joon; Kim, Chae-Lyoung; Yoon, Hye-Ji, Methods of manufacturing a magnetoresistive random access memory device.
  20. Kasko,Ihar; Kanakasabapathy,Sivananda K.; Costrini,Gregory, Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof.
  21. Choi,Hok Kin; Thirumala,Vani; Dubin,Valery; Cheng,Chin chang; Zhong,Ting, Preparation of electroless deposition solutions.
  22. Shih, Chien-Hsueh; Tsai, Minghsing; Yu, Chen-Hua; Yeh, Ming-Shih, Process for improving copper line cap formation.
  23. Shih, Chien-Hsueh; Tsai, Minghsing; Yu, Chen-Hua; Yeh, Ming-Shih, Process for improving copper line cap formation.
  24. Ngo,Minh V.; Cheng,Ning; Erhardt,Jeff P.; Ferguson,Clarence B.; Tabery,Cyrus; Caffall,John; Gottipati,Tyagamohan; Hopper,Dawn, Protection of charge trapping dielectric flash memory devices from UV-induced charging in BEOL processing.
  25. Gambino, Jeffrey P.; Stamper, Anthony K., Reducing wire erosion during damascene processing.
  26. Gambino,Jeffrey P.; Stamper,Anthony K., Reducing wire erosion during damascene processing.
  27. Cheng, Tien-Jen; Dube, Abhishek; Li, Zhengwen; Zhu, Huilong, Selective copper encapsulation layer deposition.
  28. Nogami, Takeshi; Komai, Naoki; Kito, Hideyuki; Taguchi, Mitsuru, Semiconductor device having a conductive layer with a cobalt tungsten phosphorus coating and a manufacturing method thereof.
  29. Inoue,Hiroaki; Kimura,Norio; Wang,Xinming; Matsumoto,Moriji; Kanayama,Makoto, Semiconductor device, method for manufacturing the same, and plating solution.
  30. Inoue,Hiroaki; Kimura,Norio; Wang,Xinming; Matsumoto,Moriji; Kanayama,Makoto, Semiconductor device, method for manufacturing the same, and plating solution.
  31. Yates, Donald L.; Drewes, Joel A., System having improved surface planarity for bit material deposition.
  32. Dubin,Valery M.; Cheng,Chin Chang; Hussein,Makarem; Nguyen,Phi L.; Brain,Ruth A., Use of conductive electrolessly deposited etch stop layers, liner layers and via plugs in interconnect structures.
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