IPC분류정보
| 국가/구분 |
United States(US) Patent
등록
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| 국제특허분류(IPC7판) |
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| 출원번호 |
US-0134076
(1998-08-13)
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발명자
/ 주소 |
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| 출원인 / 주소 |
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| 대리인 / 주소 |
Fliesler Dubb Meyer & Lovejoy LLP
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| 인용정보 |
피인용 횟수 :
130 인용 특허 :
11 |
초록
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A remote application on a remote computer interacts with a host application on a host computer so as to present in a remote application display window of the remote computer display a portion of the host computer screen image which intersects the foreground window of the host computer. In the prefer
A remote application on a remote computer interacts with a host application on a host computer so as to present in a remote application display window of the remote computer display a portion of the host computer screen image which intersects the foreground window of the host computer. In the preferred embodiment, a position of a moveable viewport rectangle is calculated so as to center the image of the host active window within the remote application display window if the active window rectangle's dimensions are less than the moveable viewport rectangle's dimensions; if the moveable viewport rectangle's dimensions are less than the active window rectangle's dimensions, then the new position of the moveable viewport rectangle is calculated so as to left and/or top align the moveable viewport rectangle and the active window rectangle.
대표청구항
▼
A remote application on a remote computer interacts with a host application on a host computer so as to present in a remote application display window of the remote computer display a portion of the host computer screen image which intersects the foreground window of the host computer. In the prefer
A remote application on a remote computer interacts with a host application on a host computer so as to present in a remote application display window of the remote computer display a portion of the host computer screen image which intersects the foreground window of the host computer. In the preferred embodiment, a position of a moveable viewport rectangle is calculated so as to center the image of the host active window within the remote application display window if the active window rectangle's dimensions are less than the moveable viewport rectangle's dimensions; if the moveable viewport rectangle's dimensions are less than the active window rectangle's dimensions, then the new position of the moveable viewport rectangle is calculated so as to left and/or top align the moveable viewport rectangle and the active window rectangle. oad element between a diode load and a cascode load in synchronization with said control clock. 5. The parallel AD converter according to claim 1, wherein said interpolation amplifier and said second differential amplifier in said second amplifier array are constituted by a folded cascode amplifier. 6. The parallel AD converter according to claim 1, wherein said first differential amplifier has a two-stage amplifying stage, and an output linear range of an amplifying stage at a second stage is narrower than an output linear range of an amplifying stage at a first stage. 7. The parallel AD converter according to claim 2, further comprising a sample/hold circuit for sampling said analog signal, holding it for a certain period, and then sending its hold voltage to a comparison input end of said first differential amplifier, wherein said switching unit diode-connects said load element during a sampling period of said sample/hold circuit. 8. The parallel AD converter according to claim 7, wherein said sample/hold circuit is integrated on a same substrate together with said reference voltage generator, said first amplifier array and said second amplifier array. 9. A parallel-type AD converter, comprising: a reference voltage generator for generating a plurality of reference voltages; a first amplifier array constituted by arranging first differential amplifiers, in which an analog signal is inputted to a comparison input end of each of said first differential amplifiers, a corresponding reference voltage among said plurality of reference voltages generated by said reference voltage generator is inputted to a reference input end of each of said first differential amplifiers, respectively, and each first differential amplifier has a reset switch that is controlled so as to be opened or closed by a predetermined control clock between both input ends and amplifies a potential difference between both input ends; and a second amplifier array in which complementary amplifiers, each of which interpolates and amplifies a portion between output voltages from the first differential amplifiers adjacent to each other in said first amplifier array, and second differential amplifiers, each of which amplifies the output voltage from every other first differential amplifier in said first amplifier array, are alternately arranged, wherein each of the interpolation amplifiers and the second differential amplifiers in said second amplifier array includes: a load transistor; a switching unit for selectively diode-connecting said load transistor in synchronization with said control clock; and a capacitor for keeping a voltage of said load transistor when said load-transistor is diode-connected. 10. The parallel AD converter according to claim 9, wherein said load transistor comprises cascode connected transistors, and said switching unit switches said load transistor between a diode load and a cascode load in synchronization with said control clock. 11. The parallel AD converter according to claim 9, wherein said interpolation amplifier and said second differential amplifier in said second amplifier array are constituted by a folded cascode amplifier. 12. The parallel AD converter according to claim 9, wherein said first differential amplifier has a two-stage amplifying stage, and an output linear range of an amplifying stage at a second stage is narrower than an output linear range of an amplifying stage at a first stage. 13. The parallel AD converter according to claim 10, further comprising a sample/hold circuit for sampling said analog signal, holding it for a certain period, and then sending its hold voltage to a comparison input end of said first differential amplifier, wherein said switching unit diode-connects said load transistor during a sampling period of said sample/hold circuit. 14. The parallel AD converter according to claim 13, wherein said sample/hold circuit is integrated on a same substrate together with said referen ce voltage generator, said first amplifier array and said second amplifier array. . The Micro ElectroMechanical system according to claim 1 wherein: the first torsional hinge includes a second corrugated edge. 4. The Micro ElectroMechanical system according to claim 1 wherein the first torsional hinge comprises: a plurality of wide beam sections that are characterized by a length dimension; and a plurality of narrow beam sections that alternate in position with the wide beam sections and are characterized by about the length dimension. 5. The Micro ElectroMechanical system according to claim 1 wherein: the first torsional hinge is characterized by a minimum width, and an average width, and the average width is between about 1.5 and about 7 times the minimum width. 6. The Micro ElectroMechanical system according to claim 5 wherein: the average width is between about 2 and about 5 times the minimum width. 7. The Micro ElectroMechanical system according to claim 6 wherein the first torsional hinge has: a plurality of abrupt increases in width that are interspersed with a plurality of abrupt decreases in width. 8. The Micro ElectroMechanical system according to claim 1 wherein the first torsional hinge comprises: a monocrystalline silicon material that extends at least, from the first end to the second end. 9. The Micro ElectroMechanical system according to claim 8 wherein: the monocrystalline silicon material includes an ion implanted dopant conductive pathway. 10. The Micro ElectroMechanical system according to claim 1 further comprising: an anchor coupled to the first end of the first torsional hinge; a resonant member that is dimensioned to resonate at a first frequency and is coupled to the second end of the first torsional hinge; wherein the first torsional hinge has a phase length that is equal to about an odd multiple of π/2 in a torsional mode at the first frequency. 11. The Micro ElectroMechanical system according to claim 10 wherein: the torsional hinge has a phase length that is equal to about π/2 in the torsional mode at the first frequency. 12. The Micro ElectroMechanical system according to claim 10 further comprising: a conductive pathway from the anchor, along the first torsional hinge and onto the resonant member. 13. The Micro ElectroMechanical system according to claim 10 wherein: the resonant member comprises a monocrystalline material layer; and the elongated beam comprises the monocrystalline material layer. 14. The Micro ElectroMechanical system according to claim 13 further comprising: an ion implant doped conductive pathway from the anchor, along the first torsional hinge and onto the resonant member. 15. The Micro ElectroMechanical system according to claim 10 wherein: the resonant member is a beam that extends perpendicular to the first torsional hinge and is resonant in a flexural beam mode that includes a first node; and the second end of the first torsional hinge is coupled to the beam at the first node. 16. The Micro ElectroMechanical system according to claim 15 further comprising: a conductive pathway from the anchor, along the first torsional hinge, and onto the beam. 17. The Micro ElectroMechanical system according to claim 16 wherein: the beam comprises a monocrystalline material layer; the first torsional hinge comprises the monocrystalline material layer. 18. The Micro ElectroMechanical system according to claim 17 wherein: the monocrystalline material layer includes a first semiconductor. 19. The Micro ElectroMechanical system according, to claim 17 wherein: the anchor comprises: the monocrystalline material layer; a second material layer underlying the monocrystalline material layer; and a base layer underlying the second material layer. 20. The Micro ElectroMechanical system according to claim 19 wherein: the second material layer includes an oxide; and the base layer comprises a semiconductor. 21. The Micro ElectroMechanical system according to claim 20 wherein: the monocry
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