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Method of fabricating TFTs starts with forming a nickel film selectively on a bottom layer which is formed on a substrate. An amorphous silicon film is formed on the nickel film and heated to crystallize it. The crystallized film is irradiated with infrared light to anneal it. Thus, a crystalline si

Method of fabricating TFTs starts with forming a nickel film selectively on a bottom layer which is formed on a substrate. An amorphous silicon film is formed on the nickel film and heated to crystallize it. The crystallized film is irradiated with infrared light to anneal it. Thus, a crystalline silicon film having excellent crystallinity is obtained. TFTs are built, using this crystalline silicon film.

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Method of fabricating TFTs starts with forming a nickel film selectively on a bottom layer which is formed on a substrate. An amorphous silicon film is formed on the nickel film and heated to crystallize it. The crystallized film is irradiated with infrared light to anneal it. Thus, a crystalline si

Method of fabricating TFTs starts with forming a nickel film selectively on a bottom layer which is formed on a substrate. An amorphous silicon film is formed on the nickel film and heated to crystallize it. The crystallized film is irradiated with infrared light to anneal it. Thus, a crystalline silicon film having excellent crystallinity is obtained. TFTs are built, using this crystalline silicon film. sealing part being configured such that the second surface of the ground ring is exposed therewithin. 8. The semiconductor package of claim 7 wherein the chip mounting board defines: a generally planar first board surface; a generally planar second board surface disposed in opposed relation to the first board surface; and a third board surface formed between the first and second board surfaces in opposed relation to the first board surface, the third board surface circumventing the second board surface; the semiconductor chip being attached to the first board surface of the chip mounting board. 9. The semiconductor package of claim 8 wherein each of the tie bars defines: a generally planar first tie bar surface; a generally planar second tie bar surface disposed in opposed relation to the first tie bar surface; and a third tie bar surface formed between the first and second tie bar surfaces in opposed relation to the first tie bar surface, the third tie bar surface being disposed between the frame and the ground ring. 10. The semiconductor package of claim 9 wherein each of the leads defines: a generally planar first lead surface; a generally planar second lead surface disposed in opposed relation to the first lead surface; and a third lead surface formed between the first and second third lead surfaces in opposed relation to the first lead surface, the third lead surface being oriented closer to the ground ring than the second lead surface. 11. The semiconductor package of claim 10 wherein the sealing part is configured such that the second board surface of the chip mounting board, the second ground ring surface of the ground ring, the second tie bar surface of each of the tie bars, and the second lead surface of each of the leads are exposed therewithin. 12. The semiconductor package of claim 8 wherein the semiconductor chip is attached to the first board surface via an adhesive layer. 13. The semiconductor package of claim 7 wherein the conductive wire is connected to a portion of the first ground ring surface of the ground ring which is not disposed in opposed relation to any of the third ground ring surfaces. 14. The lead frame of claim 1 wherein: the ground ring has a generally square configuration defining four segments; and the third ground ring surfaces are segregated into four sets which are disposed within respective ones of the four segments of the ground ring in equidistantly spaced intervals. 15. The lead frame of claim 14 wherein: the chip mounting board has a generally square configuration defining four peripheral edge segments; the segments of the ground ring extend along respective ones of the peripheral edge segments of the chip mounting board in spaced relation thereto; and the leads are segregated into four sets which extend toward respective ones of the segments of the ground ring. 16. The semiconductor package of claim 7 wherein: the ground ring has a generally square configuration defining four segments; and the third ground ring surfaces are segregated into four sets which are disposed within respective ones of the four segments of the ground ring in equidistantly spaced intervals. 17. The semiconductor package of claim 16 wherein: the chip mounting board has a generally square configuration defining four peripheral edge segments; the segments of the ground ring extend along respective ones of the peripheral edge segments of the chip mounting board in spaced relation thereto; and the leads are segregated into four sets which extend toward respective ones of the segments of the ground ring. 18. A semiconductor package comprising: a lead frame comprising: a chip mounting board; a ground ring circumventing the chip mounting board and defining: a generally planar first ground ring surface; a generally planar second ground ring surface disposed in opposed relation to the first ground ring surface; and a plurality of third ground ring surfaces form