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특허 상세정보

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Method of forming semiconductor device including interconnect barrier layers

특허상세정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) H01L-021/4763   
미국특허분류(USC) 438/622; 438/613; 438/627; 438/638; 438/648; 438/687
출원번호 US-0051262 (2002-01-18)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Rodriguez, Robert A.Balconi-Lamica, Michael J.
인용정보 피인용 횟수 : 68  인용 특허 : 9
초록
▼

An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24)...

대표
청구항
▼

1. A method of forming a semiconductor device comprising: forming a first interconnect overlying a semiconductor device substrate; forming a second interconnect overlying portions of the first interconnect, wherein the second interconnect is further characterized as a copper interconnect having a bond pad portion; forming a conductive barrier layer over the bond pad portion; forming an oxidation-resistant layer over the conductive barrier layer; forming a passivation layer overlying the oxidation-resistant layer; and forming a partial opening in ...

이 특허에 인용된 특허 (9)

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  4. Costrini Gregory ; Goldblatt Ronald Dean ; Heidenreich ; III John Edward ; McDevitt Thomas Leddy. Method/structure for creating aluminum wirebound pad on copper BEOL. USP2001026187680.
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  6. Kondo Ichiharu (Nagoya JPX) Noritake Chikage (Ama-gun JPX) Watanabe Yusuke (Obu JPX). Semiconductor device with bump structure. USP1997085656858.
  7. Fukuda Takuya,JPX ; Ohji Yuzuru,JPX ; Kobayashi Nobuyoshi,JPX. Semiconductor integrated circuit device and method of manufacturing same. USP2001076255151.
  8. Owada Nobuo (Ohme JPX) Oogaya Kaoru (Ohme JPX) Kobayashi Tohru (Iruma JPX) Kawaji Mikinori (Hino JPX). Semiconductor integrated circuit device in which a semiconductor chip is mounted with solder bumps for mounting to a wir. USP1993065220199.
  9. Mis Joseph Daniel ; Adema Gretchen Maerker ; Kellam Mark D. ; Rogers W. Boyd. Solder bump fabrication methods and structure including a titanium barrier layer. USP1998065767010.

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