초록 ▼

The presence/absence of an image information request signal HSYNC output from each of a plurality of display devices is monitored. Based on the monitoring result, image information stored in an image memory of a display controller incorporated in a host computer is distributed to each display device

The presence/absence of an image information request signal HSYNC output from each of a plurality of display devices is monitored. Based on the monitoring result, image information stored in an image memory of a display controller incorporated in a host computer is distributed to each display device.

대표청구항 ▼

The presence/absence of an image information request signal HSYNC output from each of a plurality of display devices is monitored. Based on the monitoring result, image information stored in an image memory of a display controller incorporated in a host computer is distributed to each display device

The presence/absence of an image information request signal HSYNC output from each of a plurality of display devices is monitored. Based on the monitoring result, image information stored in an image memory of a display controller incorporated in a host computer is distributed to each display device. he converter of claim 1, wherein each of said second stage circuits uses a double operation to convert inputted analog signal twice in said second converting rate to acquire two digital output codes in every clock. 3. The converter of claim 2, wherein said second converting rate is 1.5 times of said first converting rate. 4. The converter of claim 1, wherein said group of second stage circuits is combined every two said second stage circuit as a set of second stage circuits, said set of second stage circuits are divided into a front second stage circuit and a back second stage circuit. 5. The converter of claim 4, wherein each of said set of second stage circuits uses a recycle method to produce four digital output codes in every two clocks. 6. The converter of claim 5, wherein said recycle method comprises following steps: Said front second stage circuit converting said second analog signal to one digital output code in said second converting rate, and transmitting a second analog signal which is converted once to said back second stage circuit; Said back second stage circuit converting said second analog signal which is converted once to one digital output code and transmitting a second analog signal which is converted twice back to said front second stage circuit; Said front second stage circuit converting said second analog signal which is converted twice to one digital output code in said second converting rate, and transmitting a second analog signal which is converted three times to said back second stage circuit; Said back second stage circuit converting said second analog signal which is converted three times to one digital output code and transmitting a second analog signal which is converted four times to next group of second stage circuit. 7. The converter of claim 6, wherein said second converting rate is twice of said first converting rate. 8. A Pipelined Analog-to-Digital Converter (Pipelined ADC) used for converting a first analog signal to a digital data, said converter comprising: N first stage circuits, wherein N is a natural number, each of said N first stage circuits having a first converting rate to convert said first analog signal to N digital output codes, and generating a second analog signal; M second stage circuits series connecting after said first stage circuits, wherein M is a natural number, each of said M second stage circuits having a second converting rate which is higher than said first converting rate to convert said second analog signal to at least 2M digital output codes, and generating a third analog signal; A third stage circuit series connecting after said second stage circuits, used for converting said third analog signal to at least one digital output code; and A digital output codes integrating device, used for integrating said digital output codes converted by said first stage circuits, said second stage circuits, and said third stage circuit. 9. The converter of claim 8, wherein each of said second stage circuits uses a double operation to convert inputted analog signals twice in said second converting rate to acquire two digital output codes in every clock. 10. The converter of claim 9, wherein said second converting rate is 1.5 times of said first converting rate. 11. The converter of claim 8, wherein said M second stage circuits are combined every two said second stage circuits as a set of second stage circuits, said set of second stage circuits are divided into a front second stage circuit and a back second stage circuit. 12. The converter of claim 11, wherein each of said set of second stage circuits uses a recycle method to produce four digital output codes in every two clocks. 13. The converter of claim 11, wherein said recycle method comprises following steps: Said front second stage circuit converting said second analog signal to one digital output code in said second converting rate, and transmitting a second analog signal which is converted once to sai