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A semiconductor imaging sensor utilizes a color filter pattern. The imaging sensor includes light sensitive-elements, each of which is sensitive to photon energy in a spectral region or color band associated with the light-sensitive elements. Select light-sensitive elements in the array are sensitiv

A semiconductor imaging sensor utilizes a color filter pattern. The imaging sensor includes light sensitive-elements, each of which is sensitive to photon energy in a spectral region or color band associated with the light-sensitive elements. Select light-sensitive elements in the array are sensitive to energy in a wide band spectral region or "white" color band. This permits the capture of color information which can be lost with the use of typical semiconductor imaging sensors in digital photography. This capture of the additional color information in digital photography allows for better quality of reproduction of an image on a selected medium such as color prints.

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A semiconductor imaging sensor utilizes a color filter pattern. The imaging sensor includes light sensitive-elements, each of which is sensitive to photon energy in a spectral region or color band associated with the light-sensitive elements. Select light-sensitive elements in the array are sensitiv

A semiconductor imaging sensor utilizes a color filter pattern. The imaging sensor includes light sensitive-elements, each of which is sensitive to photon energy in a spectral region or color band associated with the light-sensitive elements. Select light-sensitive elements in the array are sensitive to energy in a wide band spectral region or "white" color band. This permits the capture of color information which can be lost with the use of typical semiconductor imaging sensors in digital photography. This capture of the additional color information in digital photography allows for better quality of reproduction of an image on a selected medium such as color prints. transition of a digital logic state (high to low; low to high). The logic state transition sensor circuit may include a sensing circuit containing sensing and amplification elements and a recording circuit containing recording elements. When a logic state transition occurs at an input of the sensing circuit, a positive logic pulse may be generated. Propagation of the logic pulse to the recording circuit causes a charge to be transferred to an output stage capacitor. Repeated logic state transitions cause similar incremental increases in the charge of the output stage capacitor. Charge transfer is governed by ratios of capacitors internal to the recording circuit and hence may be insensitive to process variation. The output stage capacitor may output a voltage representative of a number of logic state transitions sensed. fer output (OUT), and having a gate; and a first switching circuit configured for coupling the buffer input (IN) to the gate of the first pull up transistor and applying a first reference (VPRF) to the gate of the first PMOS pull up control transistor so that a voltage less than a voltage on the first power supply terminal (VDD) is applied to the source to drain path of the first pull up transistor when the first select signal is received at the first mode select input in a first state; and a second switching circuit configured for coupling the buffer input (IN) to the gate of the second pull up transistor when the first select signal is received at the first mode select input in a second state; and wherein the second voltage clamp comprises: a first NMOS pull down transistor (16) having a source to drain path coupled between the buffer output (OUT) and a second power supply terminal (VSS), and having a gate; and an first NMOS pull down control transistor (18) having a source to drain path coupling the second power supply terminal (VSS) to the source to drain path of the first NMOS pull down transistor; a second NMOS pull down transistor (22) having a source to drain path coupled between the buffer output (OUT) and the second power supply terminal (VSS), and having a gate; a third switching circuit configured for coupling the buffer input (IN) to the gate of the first pull down transistor and applying a second reference (VNRF) to the gate of the first NMOS pull down control transistor (18) so that a voltage greater than a voltage on the second power supply terminal (VSS) is applied to the source to drain path of the first pull down transistor when the second select signal is received at the second mode select input in a first state; and a fourth switching circuit configured for coupling the buffer input (IN) to the gate of the second pull down transistor when the second select signal is received at the second mode select input in a second state. 3. The buffer of claim 1, wherein the first voltage clamp comprises: a first PMOS pull up transistor (8) having a source to drain path coupled between a first power supply terminal (VDD) and the buffer output (OUT), and having a gate; and a first PMOS switching transistor (11) having a source to drain path coupling the buffer input (IN) to the gate of the first PMOS pull up transistor (8); a first NMOS cascode transistor (12) having a source to drain path coupling the buffer input (IN) to the gate of the first pull up transistor (8); a first switching circuit configured for coupling the buffer input (IN) to the gate of the first PMOS pull up transistor (8) through the first NMOS cascode transistor (12) during a high to low transition of a signal received at the buffer input (IN), and decoupling the buffer input (IN) through the source to drain path of the first PMOS switching transistor (11) during the high to low transition of the signal received at the buffer input (IN) when the first select signal is received at the first mode select input in a first state, and for coupling both the first NMOS cascode transistor (12) and the first PMOS switching transistor (11) to the buffer input (IN) during a high to low transition of a signal received at the buffer input (IN) when the first select signal is received at the first mode select input in a second state; and wherein the second voltage clamp comprises: a first NMOS pull down transistor (22) having a source to drain path coupled between the output node (OUT) and a second power supply terminal (VSS), and having a gate; a first NMOS switching transistor (19) having a source to drain path coupling the input terminal (IN) to the gate of the first NMOS pull down transistor (22); a first PMOS cascode transistor (21) having a source to drain path coupling the input terminal (IN) to the gate of the first NMOS pull down transistor (22); and a second switching circuit configured for coupling the buffer input (IN) to con trol the gate of the first NMOS pull down transistor (22) through the first PMOS cascode transistor (21) during a low to high transition of a signal received at the buffer input (IN), and decoupling the buffer input (IN) through a source to drain path of the first NMOS switching transistor (19) during a low to high transition of a signal received at the buffer input (IN) when the second select signal is received at the second mode select input in a first state, and for coupling both the first PMOS cascode transistor (21) and the first NMOS switching transistor (19) to the buffer input (IN) during a low to high transition of a signal received at the buffer input (IN) when the second select signal is applied to the second mode select input in a second state. 4. The buffer of claim 3, further comprising: a first PMOS pull up transistor (13) having a source to drain path coupled between the first power supply terminal (VDD) and the buffer output (OUT), and having a gate; a first PMOS pull up control transistor (10) having a source to drain path coupling the first power supply terminal (VDD) to the source to drain path of the first PMOS pull up transistor, and have a gate coupled to a first voltage reference (VPRF) having a voltage value less than the first power supply terminal (VDD); a first NMOS pull down transistor (16) having a source to drain path coupled between the buffer output (OUT) and the second power supply terminal (VSS), and having a gate; and an first NMOS pull down control transistor (18) having a source to drain path coupling the second power supply terminal (VSS) to the source to drain path of the first NMOS pull down transistor, and having a gate coupled to a second voltage reference (VNRF) having a voltage value greater than the second power supply terminal (VSS); and at least one inverter coupling the buffer output (OUT) to the gate of the first PMOS pull up transistor (13) and the gate of the first NMOS pull down transistor (16) at a first node (n16). 5. A buffer comprising: a first mode select input to receive a first mode select signal; a second mode select input to receive a second mode select signal; an buffer input to receive a data signal input; a buffer output; means for connecting a first power supply terminal for receiving a first voltage potential VDD to the buffer output so that a voltage on the buffer output is selectable between a first high voltage having a value less than the first voltage potential VDD and a second high voltage having a value of the first voltage potential VDD when the data signal is received in a first state, the selection between the first high voltage and the second high voltage being dependent on the first mode select signal; and means for connecting a second power supply terminal for receiving a second voltage potential VSS to the buffer output so that a voltage on the buffer output is selectable between a first low voltage having a value less than the second voltage potential VSS and a second low voltage having a value of the second voltage potential VSS when the data signal is received in a second state, the selection between the first low voltage and the second low voltage being dependent on the second mode select signal. 6. The input buffer of claim 5, wherein the means for connecting the first power supply terminal comprises: a first PMOS pull up transistor(13) having a source to drain path coupled between the first power supply terminal and the buffer output, and having a gate; a first PMOS pull up control transistor (10) having a source to drain path coupling the first power supply terminal to the source to drain path of the first PMOS pull up transistor; a second PMOS pull up transistor (8) having a source to drain path coupled between the first power supply terminal and the buffer output, and having a gate; a first switching circuit configured for coupling the input to the gate of the first pull up transistor and applying a first ref erence (VPRF) to the gate of the first PMOS pull up control transistor so that a voltage less than a voltage on the first power supply terminal is applied to the source to drain path of the first pull up transistor when the first mode select signal is in a first state; and a second switching circuit configured for coupling the input to the gate of the second pull up transistor when the first mode select signal is in a second state; wherein the means for connecting the second power supply terminal comprises: a first NMOS pull down transistor (16) having a source to drain path coupled between the buffer output and the second power supply terminal, and having a gate; an first NMOS pull down control transistor (18) having a source to drain path coupling the second power supply terminal to the source to drain path of the first NMOS pull down transistor; a second NMOS pull down transistor (22) having a source to drain path coupled between the buffer output and the second power supply terminal, and having a gate; a third switching circuit configured for coupling the input to the gate of the first pull down transistor and applying a second reference (VNRF) to the gate of the first NMOS pull down control transistor (18) so that a greater than a voltage on the second power supply terminal is applied to the source to drain path of the first pull down transistor when the second mode select signal is in a first state; and a fourth switching circuit configured for coupling the input to the gate of the second pull down transistor when a second mode select signal is in a second state. 7. The buffer of claim 5, wherein the first voltage clamp comprises: a first PMOS pull up transistor (8) having a source to drain path coupled between the first power supply terminal and the buffer output, and having a gate; and a first PMOS switching transistor (11) having a source to drain path coupling the input to the gate of the first PMOS pull up transistor (8); a first NMOS cascode transistor (12) having a source to drain path coupling the input to the gate of the first pull up transistor (8); a first switching circuit configured for coupling the input to the gate of the first PMOS pull up transistor (8) through the first NMOS cascode transistor (12) during a high to low transition of a signal received at the input, and decoupling the input through a source to drain path of the first PMOS switching transistor (11) during the high to low transition of a signal received at the input when the first mode select signal is applied in a first state, and for coupling both the first NMOS cascode transistor (12) and the first PMOS switching transistor (11) to the input during a high to low transition of the input when the first mode select signal is applied in a second state; and wherein the second voltage clamp comprises: a first NMOS pull down transistor (22) having a source to drain path coupled between the buffer output and a second power supply terminal, and having a gate; a first NMOS switching transistor (19) having a source to drain path coupling the input to the gate of the first NMOS pull down transistor (22); a first PMOS cascode transistor (21) having a source to drain path coupling the input to the gate of the first NMOS pull down transistor (22); a second switching circuit configured for coupling the input to the gate of the first NMOS pull down transistor (22) through first PMOS cascode transistor (21) during a low to high transition of a signal applied to the input, and decoupling the input through a source to drain path of the first NMOS switching transistor (19) during the low to high transition of the signal applied to the input when the second mode select signal is applied in a first state, and for coupling both the first PMOS cascode transistor (21) and the first NMOS switching transistor (19) to the input during the low to high transition of the signal applied to the input when the second mode select signal is applie