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Integrated circuit die I/O cells 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/52
  • H01L-029/40
출원번호 US-0409766 (2003-04-09)
발명자 / 주소
  • Downey, Harold A.
  • Downey, Susan H.
  • Miller, James W.
출원인 / 주소
  • Motorola, Inc.
대리인 / 주소
    Dolezal, David G.Hill, Daniel D.
인용정보 피인용 횟수 : 50  인용 특허 : 10

초록

An integrated circuit die includes an input/output (I/O) cell. The I/O cell includes active I/O circuitry in a substrate, a plurality of metal interconnect layers, an insulating layer, a first pad, and a second pad. The plurality of metal interconnect layers are formed over the substrate. The insula

대표청구항

An integrated circuit die includes an input/output (I/O) cell. The I/O cell includes active I/O circuitry in a substrate, a plurality of metal interconnect layers, an insulating layer, a first pad, and a second pad. The plurality of metal interconnect layers are formed over the substrate. The insula

이 특허에 인용된 특허 (10)

  1. Yeh Yung I,TWX ; Chao Te Tsung,TWX ; Hung Ya Ping,TWX ; Fang Hui Chin,TWX, Ball grid array package.
  2. Countryman Roger (Austin TX) Gerosa Gianfranco (Austin TX) Mendez Horacio (Austin TX), Electrostatic discharge protection device.
  3. Harvey Ian, Integrated circuit device interconnection techniques.
  4. Benedetto Vigna IT; Enrico Maria Alfonso Ravanelli IT, Integrated electronic device comprising a mechanical stress protection structure.
  5. Low Qwai H. ; Ranganathan Ramaswamy ; Torcuato Rey, Multiple row wire bonding with ball bonds of outer bond pads bonded on the leads.
  6. Shawn M. O'Connor ; Mark Allen Gerber ; Jean Desiree Miller, Packaged semiconductor with multiple rows of bond pads and method therefor.
  7. Takamori Kazuo,JPX, Semiconductor device having long pads and short pads alternated for fine pitch without sacrifice of probing.
  8. Yamada Shigeru,JPX ; Kohara Youichi,JPX, Semiconductor device having two pluralities of electrode pads, pads of different pluralities having different widths and respective pads of different pluralities having an aligned transverse edge.
  9. Shu William K. ; Payne Robert L., Staggered pad array.
  10. Bassett Stephen J., Universal I/O pad structure for in-line or staggered wire bonding or arrayed flip-chip assembly.

이 특허를 인용한 특허 (50)

  1. Bhatt, Hemanshu; Vijay, Dilip; Pallinti, Jayanthi; Sun, Sey-Shing; Ying, Hong; Kao, Chiyi, Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing.
  2. Kang, Seung H.; Krebs, Roland P.; Steiner, Kurt George; Ayukawa, Michael C.; Merchant, Sailesh Mansinh, Aluminum pad power bus and signal routing for integrated circuit devices utilizing copper technology interconnect structures.
  3. Antol, Joze E.; Osenbach, John W.; Steiner, Kurt G., Bond pad support structure for semiconductor device.
  4. Vitello, Dario; Frego, Federico; Latino, Salvatore, Bonding pad structure over active circuitry.
  5. Schwegler, Bruce; Park, Kee W.; Vesey, Jeff, Circuit board assembly and packaged integrated circuit device with power and ground channels.
  6. Scandiuzzo, Mauro; Perilli, Luca; Canegallo, Roberto, Contact and contactless differential I/O pads for chip-to-chip communication and wireless probing.
  7. Miller, James W.; Etherton, Melanie; Khazhinsky, Michael G.; Stockinger, Michael, Distributed electrostatic discharge protection circuit with varying clamp size.
  8. Mimura,Tadaaki; Hamatani,Tsuyoshi; Mizutani,Atuhito; Ueda,Kenji, Electrode pad section for external connection.
  9. Stockinger, Michael A.; Khazhinsky, Michael G.; Miller, James W., Electrostatic discharge circuit and method therefor.
  10. Venkitachalam, Girish; Rahim, Irfan; McElheny, Peter John, Integrated circuit bond pad structures.
  11. Lin, Ying-Hsi, Integrated circuit device having pads structure formed thereon and method for forming the same.
  12. Vo, Nhat D.; Tran, Tu-Anh N.; Carpenter, Burton J.; Hong, Dae Y.; Miller, James W.; Phillips, Kendall D., Integrated circuit having pads and input/output (I/O) cells.
  13. Antol, Joze Eura; Osenbach, John William; Weachock, Ronald James, Integrated circuit package including wire bonds.
  14. Kao, Ching Hung, Interconnection structure used in a pad region of a semiconductor substrate.
  15. Ko, Ching-Chung; Cheng, Tao; Liu, Tien-Yueh; Chou, Dar-Shii; Kao, Peng-Cheng, Power and ground routing of integrated circuit devices with improved IR drop and chip performance.
  16. Ko, Ching-Chung; Cheng, Tao; Liu, Tien-Yueh; Chou, Dar-Shii; Kao, Peng-Cheng, Power and ground routing of integrated circuit devices with improved IR drop and chip performance.
  17. Ko, Ching-Chung; Cheng, Tao; Liu, Tien-Yueh; Chou, Ta-Hsi; Kao, Peng-Cheng; Ke, Ling-Wei, Power and ground routing of integrated circuit devices with improved IR drop and chip performance.
  18. Ko, Ching-Chung; Cheng, Tao; Liu, Tien-Yueh; Chou, Ta-Hsi; Kao, Peng-Cheng; Ke, Ling-Wei, Power and ground routing of integrated circuit devices with improved IR drop and chip performance.
  19. Ko, Ching-Chung; Cheng, Tao; Liu, Tien-Yueh; Chou, Ta-Hsi; Kao, Peng-Cheng; Ke, Ling-Wei, Power and ground routing of integrated circuit devices with improved IR drop and chip performance.
  20. Archer, III, Vance D.; Ayukawa, Michael C.; Bachman, Mark A.; Chesire, Daniel P.; Kang, Seung H.; Kook, Taeho; Merchant, Sailesh M.; Steiner, Kurt G., Routing under bond pad for the replacement of an interconnect layer.
  21. Wang, Kun-Chih; Wu, Bing-Chang, Semiconductor chip capable of implementing wire bonding over active circuits.
  22. Wang,Kun Chih; Wu,Bing Chang, Semiconductor chip capable of implementing wire bonding over active circuits.
  23. Wang,Kun Chih; Wu,Bing Chang, Semiconductor chip capable of implementing wire bonding over active circuits.
  24. Zhang, Tianhong; Ditali, Akram, Semiconductor constructions.
  25. Zhang, Tianhong; Ditali, Akram, Semiconductor constructions, semiconductor processing methods, methods of forming contact pads, and methods of forming electrical connections between metal-containing layers.
  26. Aritome, Seiichi, Semiconductor device.
  27. Hayashi, Takahiro; Toyoshima, Shunsuke; Sakamoto, Kazuo; Morino, Naozumi; Tanaka, Kazuo, Semiconductor device.
  28. Mori, Ryo; Fukuoka, Kazuki; Morino, Naozumi; Deguchi, Yoshinori, Semiconductor device and manufacturing method for the same.
  29. Chen,Ker Min, Semiconductor device and method of manufacture thereof with two or more bond pad connections for each input/output cell.
  30. Nakayama, Sadao; Matsuura, Yoshihiro, Semiconductor device and method of manufacturing the same.
  31. Nakayama, Sadao; Matsuura, Yoshihiro, Semiconductor device and method of manufacturing the same.
  32. Satake, Nobuo, Semiconductor device and method of manufacturing the same.
  33. Satake, Nobuo, Semiconductor device and method of manufacturing the same.
  34. Satake, Nobuo, Semiconductor device and method of manufacturing the same.
  35. Ono, Naoko, Semiconductor device having a ground metal layer through which at least one hole is formed, and a ground patch disposed in the at least one hole.
  36. Tanaka, Junji, Semiconductor device having a semiconductor chip mounted on an insulator film and coupled with a wiring layer, and method for manufacturing the same.
  37. Wakabayashi, Takeshi; Mihara, Ichiro, Semiconductor device having reduced number of external pad portions.
  38. Yang, Hyang-Ja, Semiconductor device including a metal layer having a first pattern and a second pattern which together form a web structure, thereby providing improved electrostatic discharge protection.
  39. Suzuki,Takehiro, Semiconductor device using inorganic film between wiring layer and bonding pad.
  40. Oda, Noriaki, Semiconductor device with bonding pad support structure.
  41. Hayashi, Takahiro; Toyoshima, Shunsuke; Sakamoto, Kazuo; Morino, Naozumi; Tanaka, Kazuo, Semiconductor device with output circuit and pad.
  42. Hayashi, Takahiro; Toyoshima, Shunsuke; Sakamoto, Kazuo; Morino, Naozumi; Tanaka, Kazuo, Semiconductor device with output circuit and pad arrangements.
  43. Hayashi, Takahiro; Toyoshima, Shunsuke; Sakamoto, Kazuo; Morino, Naozumi; Tanaka, Kazuo, Semiconductor device with output circuit arrangement.
  44. Chen, Ker-Min, Semiconductor device with two or more bond pad connections for each input/output cell and method of manufacture thereof.
  45. Chen, Ker-Min, Semiconductor device with two or more bond pad connections for each input/output cell and method of manufacture thereof.
  46. Hayashi, Takahiro; Toyoshima, Shunsuke; Sakamoto, Kazuo; Morino, Naozumi; Tanaka, Kazuo, Semiconductor devices with output circuit and pad.
  47. Yokoyama, Kenji, Semiconductor integrated circuit device and method for designing the same.
  48. Bachman, Mark A.; Bitting, Donald S.; Chittipeddi, Sailesh; Kang, Seung H.; Merchant, Sailesh M., Solder bump structure for flip chip semiconductor devices and method of manufacturing therefore.
  49. Li, Yuan; Nath, Som; Van Dort, Maarten Jeroen, Via network structures and method therefor.
  50. Li, Yuan; Nath, Som; van Dort, Maarten, Via network structures and method therefor.
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