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Method and apparatus for selectively providing hierarchy to a circuit design 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/45
  • G06F-009/455
  • G06F-017/50
출원번호 US-0789703 (1997-01-27)
발명자 / 주소
  • Merryman, Kenneth E.
  • Lautzenheiser, Ted G.
  • Engh, Michael K.
출원인 / 주소
  • Unisys Corporation
대리인 / 주소
    Johnson, Charles A.Starr, Mark T.Nawrocki, Rooney & Sivertson PA
인용정보 피인용 횟수 : 58  인용 특허 : 45

초록

A method and apparatus for selectively providing hierarchy to a circuit design. The present invention contemplates providing a number of hierarchical statements in a description of a circuit design, wherein the syntax of the hierarchical statements allows the hierarchical statements to be visible wh

대표청구항

A method and apparatus for selectively providing hierarchy to a circuit design. The present invention contemplates providing a number of hierarchical statements in a description of a circuit design, wherein the syntax of the hierarchical statements allows the hierarchical statements to be visible wh

이 특허에 인용된 특허 (45)

  1. Takai Yuji,JPX ; Nakatani Kazue,JPX ; Matsumoto Michihiro,JPX, Apparatus and method of supporting functional design of logic circuit and apparatus and method of verifying functional.
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  11. Kamijima Shinji (Tokyo JPX), Floor-planning apparatus for hierarchical design of LSI.
  12. Seyler Mark R. (Portland OR), Graph-based programming system and associated method.
  13. Modarres Hossein (Mountain View CA) Raam Susan (Fremont CA) Lai Jiun-Hao (Santa Clara CA), Hierarchical floorplanner.
  14. Mastellone Mitchel A. (New Brunswick NJ), Hierarchical net list derivation system.
  15. Mittal Manmohan (Thousand Oaks CA), Hierarchical netlist extraction tool.
  16. Do Cuong (San Jose CA) Wei Ruey-Sing (Fremont CA), Hierarchical ordering of logical elements in the canonical mapping of net lists.
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  21. Vander Zanden Nels B. (Mountain View CA) Mahmood Mossaddeq (San Jose CA), Method and apparatus for forming an integrated circuit including a memory structure.
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  26. Rostoker Michael D. (Boulder Creek CA) Dangelo Carlos (Los Gatos CA) Watkins Daniel R. (Los Altos CA), Method and system for creating, deriving and validating structural description of electronic system from higher level, b.
  27. Kim Michelle Y. (Scarsdale NY), Method and system for providing a non-rectangular floor plan.
  28. Matsunaga Yusuke (Yokohama JPX), Method for changing an arrangement of an initial combinational circuit to satisfy prescribed delay time by computing per.
  29. Morita Masato (Hadano JPX) Ikariya Yukio (Hadano JPX) Sakataya Yoshinori (Hadano JPX) Miyoshi Masayuki (Hadano JPX), Method for generating logic circuit data.
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  32. Petrus Edwin S. (Santa Clara CA), Method for preparing and dynamically loading context files.
  33. Nishiyama Tamotsu (Hirakata JPX) Ikeda Kazushi (Tsu JPX) Matsunaga Tomoko (Kumamoto JPX), Method of and system for automatically generating network diagrams.
  34. Altheimer Michel (Antibes FRX) Gravoulet Valery F. (Valbonne FRX) Holt Paul M. (Antibes FRX) Riherd Frank T. (Nice FRX), Methods of operating cell libraries and of realizing large scale integrated circuits using a programmed compiler includi.
  35. Parham Darrell R., Methods, data structures and apparatus for traversing a hierarchical netlist.
  36. Curtin James J. (Fishkill NY), Minimizing path delay in a machine by compensation of timing through selective placement and partitioning.
  37. Lee Tsu-Chang (San Jose CA), Multiple-layer contour searching method and apparatus for circuit building block placement.
  38. Sturges Jay J. (Orangevale CA), Process oriented logic simulation having stability checking.
  39. Lee Kaiwin (Sunnyvale CA) Chung Lu (Sunnyvale CA) Lin Chin-Hsen (Milpitas CA) Liao Yuh-Zen (Saratoga CA) Wuu Stephen (Sunnyvale CA), Routing algorithm method for standard-cell and gate-array integrated circuit design.
  40. Crain Steven L. (Chandler AZ) Burkis Joseph J. (Chandler AZ) Cowan Andrew H. (Gilbert AZ) Lutz Martin F. (Mesa AZ), Rule based floorplanner.
  41. Hooper Donald F. (Northboro MA) Kundu Snehamay (Marlboro MA), Rule structure in a procedure for synthesis of logic circuits.
  42. Dangelo Carlos (Los Gatos CA) Nagasamy Vijay (Union City CA), Specification and design of complex digital systems.
  43. Putatunda Rathindra N. (Marlton NJ) Smith David C. (Williamstown NJ) McNeary Stephen A. (Somerville NJ), Structured design method for high density standard cell and macrocell layout of VLSI chips.
  44. Brasen Daniel R. (San Francisco CA) Ashtaputre Sunil V. (San Jose CA), Symbolic routing guidance for wire networks in VLSI circuits.
  45. Norton Joseph Wayne ; Blaauw David Theodore ; Jones Larry Grant, Updating hierarchical DAG representations through a bottom up method.

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  1. Mar, Monte, Apparatus and method for programmable power management in a programmable analog circuit block.
  2. Lin, Shyh-Chang; Lee, Chia-Huei; Lu, Yu-Sheng; Ho, Bang-Hwa, Automatic schematic diagram generation using topology information.
  3. Sullam, Bert; Kutz, Harold; Mar, Monte; Thiagaragen, Eashwar; Williams, Timothy; Wright, David G., Autonomous control in a programmable system.
  4. Roe, Steve; Nemecek, Craig, Breakpoint control in an in-circuit emulation system.
  5. Wright, David G.; Williams, Timothy J., Circuit and method for improving the accuracy of a crystal-less oscillator having dual-frequency modes.
  6. Synder, Warren; Sullam, Bert, Clock driven dynamic datapath chaining.
  7. Nemecek, Craig, Conditional branching in an in-circuit emulation system.
  8. Best, Andrew; Ogami, Kenneth; Zhaksilikov, Marat, Configuration of programmable IC design elements.
  9. Roesner, Wolfgang; Williams, Derek Edward, Detecting events within simulation models.
  10. Synder, Warren; Sullam, Bert, Dynamically configurable and re-configurable data path.
  11. Williams, Derek Edward; Hunt, Bryan Ronald; Roesner, Wolfgang, Embedded hardware description language instrumentation.
  12. Newton,Jim Edward; Scheiba,Christian, Encapsulating parameterized cells (pcells).
  13. Nemecek, Craig; Roe, Steve, External interface for event architecture.
  14. Pleis, Matthew A.; Ogami, Kenneth Y.; Zhaksilikov, Marat, Graphical user interface for dynamically reconfiguring a programmable device.
  15. Anderson, Doug, Graphical user interface with user-selectable list-box.
  16. Nemecek, Craig; Roe, Steve, In-circuit emulator and pod synchronized boot.
  17. Seguine, Dennis R., Input/output multiplexer bus.
  18. Sequine, Dennis R., Input/output multiplexer bus.
  19. Kamon, Kazuya, Layout data saving method, layout data converting device and graphic verifying device.
  20. Kamon,Kazuya, Layout data saving method, layout data converting device and graphic verifying device.
  21. Moyal, Nathan; Stiff, Jonathon, Method and circuit for rapid alignment of signals.
  22. Perrin, Jon; Seguine, Dennis, Method for parameterizing a user module.
  23. Snyder, Warren S.; Mar, Monte, Microcontroller programmable system on a chip.
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  25. Snyder, Warren S.; Mar, Monte, Microcontroller programmable system on a chip.
  26. Snyder, Warren, Microcontroller programmable system on a chip with programmable interconnect.
  27. Snyder, Warren S, Microcontroller programmable system on a chip with programmable interconnect.
  28. McDonald, John; Pearson, Jon; Ogami, Kenneth; Anderson, Doug, Model for a hardware device-independent method of defining embedded firmware for programmable systems.
  29. McDonald, John; Pearson, Jon; Ogami, Kenneth; Anderson, Doug, Model for a hardware device-independent method of defining embedded firmware for programmable systems.
  30. Kutz, Harold, Numerical band gap.
  31. Snyder, Warren S.; Mar, Monte, PSOC architecture.
  32. Snyder, Warren; Mar, Monte, PSOC architecture.
  33. Snyder, Warren S.; Mar, Monte, PSoC architecture.
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  35. Ogami, Kenneth Y., Power management architecture, method and configuration system.
  36. Ogami, Kenneth Y., Power management architecture, method and configuration system.
  37. Snyder, Warren, Programmable microcontroller architecture.
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  40. Thiagarajan, Eashwar; Sivadasan, Mohandas Palatholmana; Rohilla, Gajender; Kutz, Harold; Mar, Monte, Programmable sigma-delta analog-to-digital converter.
  41. Snyder, Warren; Maheshwari, Dinesh; Ogami, Kenneth; Hastings, Mark, Providing hardware independence to automate code generation of processing device firmware.
  42. Pleis, Matthew A.; Sullam, Bert; Lesher, Todd, Reconfigurable testing system and method.
  43. Nemecek, Craig, Sleep and stall in an in-circuit emulation system.
  44. Nayak, Anshuman; Chakrabarti, Samantak; Agrawal, Brijesh; Sachan, Nilam, System and method for altering circuit design hierarchy to optimize routing and power distribution using initial RTL-level circuit description netlist.
  45. Ogami, Kenneth; Best, Andrew; Zhaksilikov, Marat, System and method for controlling a target device.
  46. Anderson, Douglas H.; Ogami, Kenneth Y., System and method for dynamically generating a configuration datasheet.
  47. Ogami, Kenneth Y.; Hood, Frederick R., System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit.
  48. Ogami, Kenneth Y.; Hood, III, Frederick R., System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit.
  49. Nayak,Anshuman; Haldar,Malay; Choudhary,Alok; Saxena,Vikram; Banerjee,Prithviraj, System for architecture and resource specification and methods to compile the specification onto hardware.
  50. Sullam, Bert; Snyder, Warren; Mohammed, Haneef, System level interconnect with programmable switching.
  51. Sullam, Bert; Snyder, Warren; Mohammed, Haneef, System level interconnect with programmable switching.
  52. Beattie,Michael W.; Pileggi,Lawrence T., Systems, methods and computer program products for creating hierarchical equivalent circuit models.
  53. Ogami, Kenneth Y.; Anderson, Doug; Pleis, Matthew; Hood, III, Frederick Redding, Techniques for generating microcontroller configuration information.
  54. Ogami, Kenneth Y.; Anderson, Doug; Pleis, Matthew; Hood, Rick, Techniques for generating microcontroller configuration information.
  55. Venkataraman, Garthik; Kutz, Harold; Mar, Monte, Temperature sensor with digital bandgap.
  56. Beard, Paul; Woodings, Ryan Winfield, Touch wake for electronic devices.
  57. Bartz, Manfred; Zhaksilikov, Marat; Anderson, Doug, User interface for efficiently browsing an electronic document using data-driven tabs.
  58. Sivadasan, Mohandas Palatholmana; Rohilla, Gajendar, Voltage controlled oscillator delay cell and method.
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