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A system, method, and computer program product for allowing a pilot to view weather hazards at a selected altitude or within a range of altitudes. The weather display system includes a memory, a processor, and a display device. The memory stores radar return data in a three-dimensional buffer. The p

A system, method, and computer program product for allowing a pilot to view weather hazards at a selected altitude or within a range of altitudes. The weather display system includes a memory, a processor, and a display device. The memory stores radar return data in a three-dimensional buffer. The processor is coupled to the memory and retrieves radar return data stored in the three-dimensional buffer that corresponds to an altitude. The processor generates an image of the retrieved radar return data. The display device displays the generated image.

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A system, method, and computer program product for allowing a pilot to view weather hazards at a selected altitude or within a range of altitudes. The weather display system includes a memory, a processor, and a display device. The memory stores radar return data in a three-dimensional buffer. The p

A system, method, and computer program product for allowing a pilot to view weather hazards at a selected altitude or within a range of altitudes. The weather display system includes a memory, a processor, and a display device. The memory stores radar return data in a three-dimensional buffer. The processor is coupled to the memory and retrieves radar return data stored in the three-dimensional buffer that corresponds to an altitude. The processor generates an image of the retrieved radar return data. The display device displays the generated image. tion differential voltages and extrapolation differential voltages to a first and a second differential input voltages, comprising: a first differential amplifier for inputting the first differential input voltage and generating a differential output voltage between an inverted output terminal and a non-inverted terminal thereof; a second differential amplifier for inputting the second differential input voltage and generating a differential output voltage between an inverted output terminal and a non-inverted terminal thereof; a first voltage dividing element array (NT1) disposed between the non-inverted output terminals of the first and the second differential amplifiers; a second voltage dividing element array (NT2) disposed between the inverted output terminals of the first and the second differential amplifiers; a fifth voltage dividing element array (NT5) disposed between the non-inverted output terminal of the first differential amplifier and the inverted output terminal of the second differential amplifier; and a sixth voltage dividing element array (NT6) disposed between the inverted output terminal of the first differential amplifier and the non-inverted output terminal of the second differential amplifier; wherein the interpolation differential voltages are generated from nodes in the first voltage dividing element array and from nodes in the second voltage dividing element array, and the extrapolation differential voltages are generated from between nodes in the fifth voltage dividing element array and in the sixth voltage dividing element array. 5. The interpolation circuit according to claim 4, wherein each of the first and the second voltage dividing element arrays has N voltage dividing elements connected in series, and each corresponding connection nodes of the voltage dividing elements thereof are connected respectively to each corresponding one of N-1 interpolation output terminal pairs, so that the interpolation differential voltages are output from the interpolation output terminal pairs, and wherein each of the fifth and the sixth voltage dividing element arrays has a plurality of voltage dividing elements connected in series, each corresponding connection nodes of the voltage dividing elements thereof are connected respectively to the first and second extrapolation output terminal pairs, so that the extrapolation differential voltages being output from the extrapolation output terminal pairs. 6. An A/D conversion circuit comprising: the interpolation circuit according to claim 4 or 5; and a comparator array for inputting respectively the interpolation differential voltages and the extrapolation differential voltages so as to detect the polarity of the differential voltages. 7. An interpolation circuit for generating interpolation differential voltages and extrapolation differential voltages to a first and a second differential input voltages, comprising: a first differential amplifier for inputting the first differential input voltage and generating a differential output voltage between an inverted output terminal and a non-inverted terminal thereof; a second differential amplifier for inputting the second differential input voltage and generating a differential output voltage between an inverted output terminal and a non-inverted terminal thereof; a seventh voltage dividing element array (NT7) disposed between the non-inverted output terminals of the first and the second differential amplifiers; an eighth voltage dividing element array (NT8) disposed between the inverted output terminals of the first and the second differential amplifiers; a ninth voltage dividing element array (NT9) disposed between a first node in the seventh voltage dividing element array and a second node in the eighth voltage dividing element array; and a tenth voltage dividing element array (NT10) disposed between a second node in the seventh voltage dividing element array and a first node in the e