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A method of passing information between two or more information handling devices is described. Such information handling devices might be a printer 342, a personal computer 343, or a scanner 344. Means for communication of information between information handling devices in the form of a network 341

A method of passing information between two or more information handling devices is described. Such information handling devices might be a printer 342, a personal computer 343, or a scanner 344. Means for communication of information between information handling devices in the form of a network 341 and network connection means 345 exist. The information transmitted comprises a data format hierarchy, wherein a device intended to receive transmitted data evaluates the data format hierarchy and determines the format in which the data is then received thereby. Advantageously, the receiving device determines the format in which the data is then received by a response to the transmitting device comprising a path through the data format hierarchy, and all data formats comprise one or more of a plurality of data format types, and wherein for each data format type, there exists a data format receivable by all information handling devices supporting that data format type. It is advantageous in implementation if the method of passing information further comprises requests for content data for a chosen path through the data format hierarchy and responses to such requests.

대표청구항 ▼

A method of passing information between two or more information handling devices is described. Such information handling devices might be a printer 342, a personal computer 343, or a scanner 344. Means for communication of information between information handling devices in the form of a network 341

A method of passing information between two or more information handling devices is described. Such information handling devices might be a printer 342, a personal computer 343, or a scanner 344. Means for communication of information between information handling devices in the form of a network 341 and network connection means 345 exist. The information transmitted comprises a data format hierarchy, wherein a device intended to receive transmitted data evaluates the data format hierarchy and determines the format in which the data is then received thereby. Advantageously, the receiving device determines the format in which the data is then received by a response to the transmitting device comprising a path through the data format hierarchy, and all data formats comprise one or more of a plurality of data format types, and wherein for each data format type, there exists a data format receivable by all information handling devices supporting that data format type. It is advantageous in implementation if the method of passing information further comprises requests for content data for a chosen path through the data format hierarchy and responses to such requests. he signature analyzer through a plurality of word lines; decoding the address using the address decoder; and triggering the signature analyzer with the clock to latch the state of the plurality of word lines connected to the inputs of the signature analyzer. 9. The method of claim 8, further comprising examining the output of the signature analyzer for each address decoded to determine if the correct word line was turned on, and to determine if any other word line was turned on for that address. 10. The method of claim 8, further comprising examining the output of the signature analyzer for a plurality of addresses decoded to determine if the correct word line was turned on, and to determine if any other word line was turned on for all of the plurality of addresses. 11. The method of claim 8, further comprising setting the timing of the clock to a plurality of different settings to determine which ones of the plurality of word lines operate more slowly. 12. The method of claim 8, further comprising setting the timing of the clock so that the plurality of word lines are tested at a desired operating speed. 13. An apparatus, comprising: an address decoder; a signature analyzer; a plurality of circuits organized into a two-dimensional array comprising a first circuit, a second circuit, a third circuit and a fourth circuit; a first word line coupled to the address decoder, the signature analyzer, the first circuit and the second circuit; and a second word line coupled to the address decoder, the signature analyzer, the third circuit and the fourth circuit. 14. The apparatus of claim 13, wherein the address decoder decodes at least a portion of a memory address. 15. The apparatus of claim 13, wherein the first, second, third and fourth circuits are memory cells. 16. The apparatus of claim 13, wherein the first, second, third and fourth circuits are programmable logic devices. 17. The apparatus of claim 13, wherein the address decoder and the signature analyzer are connected to opposite ends of the first and second word lines. 18. The apparatus of claim 13, wherein the signature analyzer latches the state of at least one of the plurality of word lines in response to a clock. 19. The apparatus of claim 18, wherein the timing of the clock is adjustable. ir is provided with minimal bevels. 4. Circuit arrangement for reading out binary memory cell signals from a memory cell array and for storing binary memory cell signals in a memory cell array, having: a) a plurality of bit line pairs for connecting a plurality of memory cells of a memory cell array to at least one memory cell array switching transistor pair, wherein the bit line pairs are arranged to run rectilinearly and to have minimal bevels; b) a plurality of sense amplifiers connected to the memory cell array switching transistor pair, said sense amplifiers being arranged symmetrically with respect to the bit line pairs; c) at least one local data line switching transistor pair for switching the binary output signals of the sense amplifiers to at least one local data line pair; and d) at least one main data line switching transistor pair for connecting the local data line pair to at least one main data line pair arranged in through-plating regions. 5. Circuit arrangement for reading out and for storing binary memory cell signals according to claim 4, wherein the main data line switching transistor pair switches through a binary intermediate signal on a local data line pair to at least one main data line pair. 6. Circuit arrangement for reading out and for storing binary memory cell signals according to claim 4, wherein the main data line switching transistor pair is arranged in the through-plating regions. 7. Circuit arrangement for reading out and for storing binary memory cell signals according to claim 4, wherein the bit line pairs, the main data line pairs and the column control lines run parallel to one another and have a minimum distance from one another corresponding to a signal-to-noise ratio between the individual lines. 8. Circuit arrangement for reading out and for storing binary memory cell signals according to claim 4, wherein the local data line pairs, the memory cell array control lines and the row control lines run parallel to one another and perpendicularly to the bit line pairs, the main data line pairs and the column control lines and have a minimum distance from one another corresponding to a signal-to-noise ratio between the individual lines. 9. Circuit arrangement for reading out and for storing binary memory cell signals according to claim 4, wherein a section of at least one local data line pair extends over a length of at least one memory cell array. 0200, Paterson et al.; US-5041886, 19910800, Lee; US-5106772, 19920400, Lai; US-5147816, 19920900, Gill; US-5371031, 19941200, Gill; US-5394002, 19950200, Peterson; US-5457652, 19951000, Brahmbhatt, 365/185.27; US-5469383, 19951100, McElroy; US-5473179, 19951200, Hong; US-5523249, 19960600, Gill; US-5565371, 19961000, Gill; US-5646886, 19970700, Brahmbhatt; US-5670805, 19970900, Hammerl; US-5751039, 19980500, Kauffman; US-5787457, 19980700, Miller; US-5808336, 19980900, Miyawaki; US-5831301, 19981100, Horak; US-5850093, 19981200, Tarng; US-5986934, 19991100, Kao; US-6017795, 20000100, Hsieh; US-6025224, 20000200, Gall; US-6026465, 20000200, Mills; US-6040210, 20000300, Burns, Jr.; US-6077745, 20000600, Burns, Jr.; US-6093606, 20000700, Lin; US-6103577, 20000800, Horng; US-6137133, 20001000, Kauffman; US-6141247, 20001000, Roohparvar; US-6147378, 20001100, Liu; US-6157574, 20001200, Kalnitsky; US-6159803, 20001200, Hong