초록 ▼

Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Trenches and contact vias are formed in insulating layers. The trenches and vias are exposed to alternating chemistries to form monolayers of a desired lining material. Exemplary process flow

Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Trenches and contact vias are formed in insulating layers. The trenches and vias are exposed to alternating chemistries to form monolayers of a desired lining material. Exemplary process flows include alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with nitrogen. Near perfect step coverage allows minimal thickness for a diffusion barrier function, thereby maximizing the volume of a subsequent filling metal for any given trench and via dimensions.

대표청구항 ▼

Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Trenches and contact vias are formed in insulating layers. The trenches and vias are exposed to alternating chemistries to form monolayers of a desired lining material. Exemplary process flow

Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Trenches and contact vias are formed in insulating layers. The trenches and vias are exposed to alternating chemistries to form monolayers of a desired lining material. Exemplary process flows include alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with nitrogen. Near perfect step coverage allows minimal thickness for a diffusion barrier function, thereby maximizing the volume of a subsequent filling metal for any given trench and via dimensions. vely etching the silicon oxynitride region; and,(f) after performing the wet chemical process, forming spacers around the gate structure.16. A method as in claim 15 wherein in step (b) the gate material is amorphous silicon.17. A method as in claim 15 wherein in step (e) the wet chemical process is a hot phosphoric acid etch.18. A method as in claim 15 wherein in step (e) the wet chemical process is a neutral oxide etch.19. A method as in claim 15 wherein step (e) is performed before a lightly doped drain is implanted.20. A method as in claim 15 wherein step (e) is performed after a lightly doped drain is implanted.