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Semiconductor device with internal bonding pad 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/52
  • H01L-029/40
출원번호 US-0136533 (2002-05-02)
우선권정보 JP-0336202 (2001-11-01)
발명자 / 주소
  • Izumitani, Junko
  • Takewaka, Hiroki
출원인 / 주소
  • Renesas Technology Corp.
대리인 / 주소
    Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
인용정보 피인용 횟수 : 47  인용 특허 : 1

초록

A semiconductor device has a multilayer interconnection structure in which a plurality of interconnection layers is formed in an insulating film. The multilayer interconnection structure has a first metal film made of a first material and functioning as a first interconnection belonging to an interc

대표청구항

1. A semiconductor device comprising a multilayer interconnection structure in which a plurality of interconnection layers are formed in an insulating film, said multilayer interconnection structure having,a first metal film made of a first material and functioning as a first interconnection belongi

이 특허에 인용된 특허 (1)

  1. Moslehi Mehrdad M., Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics.

이 특허를 인용한 특허 (47)

  1. Mimura,Tadaaki; Hamatani,Tsuyoshi; Mizutani,Atuhito; Ueda,Kenji, Electrode pad section for external connection.
  2. Kushiyama,Kazunari; Okada,Tetsuya; Oikawa,Makoto, Insulated gate semiconductor device and manufacturing method thereof.
  3. Barth, Hans-Joachim; Holz, Juergen, Integrated circuit with intergrated capacitor and methods for making same.
  4. Pfuetzner, Ronny; Heinrich, Jens, Metallization systems of semiconductor devices comprising a copper/silicon compound as a barrier material.
  5. Sidhwa, Ardeshir J., Method and structure of a thick metal layer using multiple deposition chambers.
  6. Sidhwa, Ardeshir J., Method and structure of a thick metal layer using multiple deposition chambers.
  7. Xiao, De Yuan; Chen, Guo Qing, Method and system for forming conductive bumping with copper interconnection.
  8. Xiao, De Yuan; Chen, Guo Qing, Method and system for forming conductive bumping with copper interconnection.
  9. Xiao, De Yuan; Chen, Guo Qing, Method and system for forming conductive bumping with copper interconnection.
  10. Isozaki, Seiya; Moriyama, Takashi; Maeda, Takehiko, Method of manufacturing semiconductor device.
  11. Honma, Takuro; Takata, Yoshifumi, Method of manufacturing semiconductor device having surface protective films on bond pad.
  12. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  13. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  14. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  15. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  16. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  17. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  18. Huang, Rui; Wo, Chun Hong; DiMaano, Antonio Jr. Bambalan, Reliable interconnect.
  19. Wang, Kun-Chih; Wu, Bing-Chang, Semiconductor chip capable of implementing wire bonding over active circuits.
  20. Wang,Kun Chih; Wu,Bing Chang, Semiconductor chip capable of implementing wire bonding over active circuits.
  21. Wang,Kun Chih; Wu,Bing Chang, Semiconductor chip capable of implementing wire bonding over active circuits.
  22. Wu,Bing Chang, Semiconductor chip capable of implementing wire bonding over active circuits.
  23. Wu,Bing Chang; Wang,Kun Chih; Chao,Mei Ling; Chen,Shiao Shien, Semiconductor chip capable of implementing wire bonding over active circuits.
  24. Wu,Bing Chang; Wang,Kun Chih; Chao,Mei Ling; Chen,Shiao Shien, Semiconductor chip capable of implementing wire bonding over active circuits.
  25. Sato, Hideo, Semiconductor device.
  26. Yu, Dong-Hee; Suh, Bong-Seok; Kim, Yoon-Hae; Kwon, O Sung; Kwon, Oh-Jung, Semiconductor device.
  27. Iwamoto, Takeshi; Kono, Kazushi; Arakawa, Masashi; Yonezu, Toshiaki; Obayashi, Shigeki, Semiconductor device and a method increasing a resistance value of an electric fuse.
  28. Iwamoto, Takeshi; Kono, Kazushi; Arakawa, Masashi; Yonezu, Toshiaki; Obayashi, Shigeki, Semiconductor device and a method increasing a resistance value of an electric fuse.
  29. Iwamoto, Takeshi; Kono, Kazushi; Arakawa, Masashi; Yonezu, Toshiaki; Obayashi, Shigeki, Semiconductor device and a method of increasing a resistance value of an electric fuse.
  30. Nose, Fujiaki; Kikuchi, Hiroshi; Ueno, Satoshi; Nakazato, Norio, Semiconductor device and a method of manufacturing the same.
  31. Nose,Fujiaki; Kikuchi,Hiroshi; Ueno,Satoshi; Nakazato,Norio, Semiconductor device and a method of manufacturing the same.
  32. Watanabe, Kenichi; Ikeda, Masanobu; Kimura, Takahiro, Semiconductor device and method for manufacturing the same.
  33. Yamagata, Takahiro, Semiconductor device and method for manufacturing the same.
  34. Obayashi, Shigeki; Yonezu, Toshiaki; Iwamoto, Takeshi; Kono, Kazushi; Arakawa, Masashi; Uchida, Takahiro, Semiconductor device having electrical fuses with less power consumption and interconnection arrangement.
  35. Obayashi, Shigeki; Yonezu, Toshiaki; Iwamoto, Takeshi; Kono, Kazushi; Arakawa, Masashi; Uchida, Takahiro, Semiconductor device having electrical fuses with less power consumption and interconnection arrangement.
  36. Homma, Takuro; Takata, Yoshifumi, Semiconductor device having surface protective films on bond pad.
  37. Grillberger, Michael; Lehr, Matthias, Semiconductor device including stress relaxation gaps for enhancing chip package interaction stability.
  38. Suzuki,Takehiro, Semiconductor device using inorganic film between wiring layer and bonding pad.
  39. Hotta, Katsuhiko; Sasahara, Kyoko; Hayamizu, Taichi; Kawano, Yuichi, Semiconductor device with a fuse formed by a damascene technique and a method of manufacturing the same.
  40. Hotta, Katsuhiko; Sasahara, Kyoko; Hayamizu, Taichi; Kawano, Yuichi, Semiconductor device with a fuse formed by a damascene technique and a method of manufacturing the same.
  41. Hotta, Katsuhiko; Sasahara, Kyoko; Hayamizu, Taichi; Kawano, Yuichi, Semiconductor device with fuse and a method of manufacturing the same.
  42. Chang, Shih-Ming; Hsieh, Ken-Hsien; Ou, Tsong-Hua; Liu, Ru-Gun; Fan, Fang-Yu; Hou, Yuan-Te, Semiconductor device with self-aligned interconnects and blocking portions.
  43. Lim, Yeow Kheng; See, Alex; Lee, Tae Jong; Vigar, David; Hsia, Liang Choo; Pey, Kin Leong, Slot designs in wide metal lines.
  44. Briggs, Benjamin D.; Clevenger, Lawrence A.; Motoyama, Koichi; Rizzolo, Michael, Structure and fabrication method for electromigration immortal nanoscale interconnects.
  45. Lin, Jing-Cheng, Thermal dissipation through seal rings in 3DIC structure.
  46. Tang, Yu-Po; Chang, Shih-Ming; Hsieh, Ken-Hsien; Liu, Ru-Gun, Via-free interconnect structure with self-aligned metal line interconnections.
  47. Tang, Yu-Po; Chang, Shih-Ming; Hsieh, Ken-Hsien; Liu, Ru-Gun, Via-free interconnect structure with self-aligned metal line interconnections.
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