IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0344608
(1999-06-25)
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발명자
/ 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
Blakely, Sokoloff, Taylor & Zafman LLP
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인용정보 |
피인용 횟수 :
22 인용 특허 :
97 |
초록
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System and method in a network processor for performing cut-through forwarding of LANE packets without incurring the overhead associated with LANE protocol stack assisted routing. A content addressable memory (CAM) stores LEC uplink information including mapping between MAC destination addresses and
System and method in a network processor for performing cut-through forwarding of LANE packets without incurring the overhead associated with LANE protocol stack assisted routing. A content addressable memory (CAM) stores LEC uplink information including mapping between MAC destination addresses and VCC information. The network processor also stores LEC information table for corresponding VLAN identifiers and LECs. The LEC information table includes LEC ID information for the VLAN ID. For a LANE packet received from Ethernet and outbound to ATM destination, the network processor determines the LEC ID for the packet and then performs a CAM lookup to determine VCC information for the packet. The packet is then forwarded using the LEC ID and VCC information. For a LANE packet received from an ATM source and outbound to the Ethernet, the network processor determines the interface address of the packet. Based on the interface address, the network processor determines if the packet is a echoed or loopback packet or if its destination is the network processor itself. The packet is then routed to via the Ethernet if it is not a loopback or echo packet and the destination is not the network processor.
대표청구항
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System and method in a network processor for performing cut-through forwarding of LANE packets without incurring the overhead associated with LANE protocol stack assisted routing. A content addressable memory (CAM) stores LEC uplink information including mapping between MAC destination addresses and
System and method in a network processor for performing cut-through forwarding of LANE packets without incurring the overhead associated with LANE protocol stack assisted routing. A content addressable memory (CAM) stores LEC uplink information including mapping between MAC destination addresses and VCC information. The network processor also stores LEC information table for corresponding VLAN identifiers and LECs. The LEC information table includes LEC ID information for the VLAN ID. For a LANE packet received from Ethernet and outbound to ATM destination, the network processor determines the LEC ID for the packet and then performs a CAM lookup to determine VCC information for the packet. The packet is then forwarded using the LEC ID and VCC information. For a LANE packet received from an ATM source and outbound to the Ethernet, the network processor determines the interface address of the packet. Based on the interface address, the network processor determines if the packet is a echoed or loopback packet or if its destination is the network processor itself. The packet is then routed to via the Ethernet if it is not a loopback or echo packet and the destination is not the network processor. or the low clock frequency at a first final value determined on the basis of a predetermined first final trimming value used for trimming, after an activation of the first clock frequency generator and, immediately thereafter,g) restarting the counter for the high clock frequency from the intermediate value; andh) stopping the counter for the high clock frequency at a second final value determined on the basis of a reference value, obtained during trimming, for the high clock frequency.2. The method according to claim 1, wherein the step of trimming the low and high clock frequencies comprises:a1) starting the counter for the fast clock frequency concurrently with a reference counter for the high clock frequency;a2) stopping the counter for the high clock frequency in dependence on the low clock frequency, defining an intermediate trimming value and, immediately thereafter,a3) starting the counter for the low clock frequency;a4) stopping the counter for the high clock frequency at the predetermined first final trimming value and, immediately thereafter;a5) restarting the counter for the high clock frequency from the intermediate trimming value; anda6) stopping the counter for the high clock frequency concurrently with the reference counter for the high clock frequency at a second final trimming value predetermined for the reference counter and corresponding to the trimming time period, wherein a count of the counter for the high clock frequency is defined as the reference value for the high clock frequency.3. The method according to claim 2, which comprises stopping the counter for the high clock frequency in one of steps c) and a2) at a next positive flank of the low clock frequency after the starting of the counter for the high clock frequency.4. The method according to claim 1, wherein the low clock frequency is a clock frequency in a mobile station of a mobile radio system and the high clock frequency is a system clock frequency in the mobile radio system.5. The method according to claim 4, wherein the mobile radio system is based on the GSM Standard, a length of the changeover time period is an integer multiple m of a GSM frame length, and a length of the trimming time period is an integer multiple n of the GSM frame length.6. The method according to claim 5, which comprises determining the first final value by dividing the predetermined first final trimming value by n and by multiplying the value by m, and wherein the second final value is determined by dividing the reference value obtained during trimming by n and by multiplying the value by m.7. The method according to claim 6, which comprises multiplying with m a division remainder that occurs when dividing the first and/or second final value by n and, immediately after step h), starting a remainder counter and stopping the remainder counter at the division remainder multiplied by m.8. An apparatus for maintaining a time reference governed by a high clock frequency, in which a changeover is made to a low clock frequency for a specific changeover time period, comprising: a high clock frequency generator for a relatively high clock frequency;a low clock frequency generator for a relatively low clock frequency;a counter for the high clock frequency connected to said high clock frequency generator;a counter for the low clock frequency connected to said low clock frequency generator; anda sequence controller connected to said counter for the high clock frequency and to said counter for the low clock frequency, said sequence controller:a) trimming the low and high clock frequencies during a trimming time period;b) starting said counter for the high clock frequency;c) stopping said counter for the high clock frequency in dependence on the low clock frequency, defining an intermediate value and, immediately thereafter,d) starting said counter for the low clock frequency;e) deactivating said first clock frequency generator;f) stopping said counter for the low clock frequency at a first final value, determined on a basis of a predetermined first final trimming value used for trimming, after the activation of said first clock frequency generator and, immediately thereafter,g) restarting said counter for the high clock frequency from the intermediate value; andh) stopping said counter for the high clock frequency at a second final value, determined on a basis of a reference value, obtained during trimming, for the high clock frequency.9. The apparatus according to claim 8, which further comprises a reference counter for the high clock frequency, and wherein said sequence controller is programmed to carry out the following steps during trimming of the low and high clock frequencies:a1) starting said counter for the high clock frequency concurrently with said reference counter for the high clock frequency;a2) stopping said counter for the high clock frequency as a function of the low clock frequency, defining an intermediate trimming value and, immediately thereafter;a3) starting said counter for the low clock frequency;a4) stopping said counter for the low clock frequency at the predetermined first final trimming value and, immediately thereafter,a5) restarting said counter for the high clock frequency from the intermediate trimming value; anda6) stopping said counter for the high clock frequency concurrently with said reference counter for the high clock frequency at a second final trimming value predetermined for the reference counter and corresponding to the trimming time period, wherein a count of said counter for the high clock frequency is defined as the reference value for the high clock frequency.10. The apparatus according to claim 8, wherein said sequence controller is programmed to stop said counter for the high clock frequency in one of step c) and step a2) at a next positive flank of the low clock frequency after starting of said counter for the high clock frequency.11. In combination with a mobile station in a mobile radio system, the apparatus according to claim 8.12. The combination according to claim 11, wherein the mobile radio system is based on the GSM Standard, and a length of the changeover time period is an integer multiple m of the GSM frame length, and a length of the trimming time period is an integer multiple n of the GSM frame length.13. The combination according to claim 12, wherein said sequence controller is programmed to determine the first final value by dividing the predetermined first final trimming value by n and by multiplying it by m, and to determine the second final value by dividing the reference value obtained during trimming by n and by multiplying by m.14. The combination according to claim 13, which further comprises a remainder counter, and wherein said sequence controller is programmed to multiply by m a division remainder resulting from dividing the first and/or second final value by n, and, immediately after processing step h), to start said remainder counter and to stop said remainder counter at the division remainder multiplied by m.
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