초록 ▼

A programmable interface. The inventive interface is designed to be used with an interface controller and includes a first circuit for selecting one or more components from a plurality of components in response to at least one first control signal. A second circuit selectively connects the component

A programmable interface. The inventive interface is designed to be used with an interface controller and includes a first circuit for selecting one or more components from a plurality of components in response to at least one first control signal. A second circuit selectively connects the components in response to at least one second control signal. A third circuit selects a serial output mode or a parallel output mode of said components in response to at least one third control signal. In an illustrative implementation, the inventive interface is used as part of an IEEE 1149.1 bus architecture and includes a plurality of stages. At least one of the stages is associated with each of the components under test and includes circuitry for selecting an associated component. The second circuit includes circuitry within each stage for selectively connecting an associated component to a second component by outputting the output of an associated component or the output a previous stage as the output of the stage. The third circuit includes circuitry disposed within each stage for selecting between a serial or parallel mode of operation by outputting the output of a previous stage or a test data output from a bus controller as the test data output from the stage. The first, second and third control signals are provided by the interface controller. The inventive interface thereby provides a system and technique for conducting tests of components in an 1149.1 environment on a single ring so that standard COTS test generation tools can be used, while also allowing run-based commands to be executing on some components while at the same time communicating with other components.

대표청구항 ▼

A programmable interface. The inventive interface is designed to be used with an interface controller and includes a first circuit for selecting one or more components from a plurality of components in response to at least one first control signal. A second circuit selectively connects the component

A programmable interface. The inventive interface is designed to be used with an interface controller and includes a first circuit for selecting one or more components from a plurality of components in response to at least one first control signal. A second circuit selectively connects the components in response to at least one second control signal. A third circuit selects a serial output mode or a parallel output mode of said components in response to at least one third control signal. In an illustrative implementation, the inventive interface is used as part of an IEEE 1149.1 bus architecture and includes a plurality of stages. At least one of the stages is associated with each of the components under test and includes circuitry for selecting an associated component. The second circuit includes circuitry within each stage for selectively connecting an associated component to a second component by outputting the output of an associated component or the output a previous stage as the output of the stage. The third circuit includes circuitry disposed within each stage for selecting between a serial or parallel mode of operation by outputting the output of a previous stage or a test data output from a bus controller as the test data output from the stage. The first, second and third control signals are provided by the interface controller. The inventive interface thereby provides a system and technique for conducting tests of components in an 1149.1 environment on a single ring so that standard COTS test generation tools can be used, while also allowing run-based commands to be executing on some components while at the same time communicating with other components. essor for an information processing equipment, as defined in the claim 1, wherein said plural write data is transferred from said system bus through a bus converter to a bus being different from said system bus.4. A processor for an information processing equipment, as defined in the claim 1, further comprising means for initializing the transfer of write data with a delay of a predetermined time period, when there are detected the write addresses in succession within said write address buffer by said comparator.5. A processor for an information processing equipment, as defined in the claim 1, further comprising means for setting up a value of said predetermined time period selectively.6. A processor for an information processing equipment, as defined in the claim 1, wherein said processor is integrated on a single chip.7. A processor for an information processing equipment, executing calculation processes, being connected with a multiplex bus with which address and data are used in time-sharing manner, comprising: a write address buffer for storing plural write addresses which are transmitted with use of said multiplex bus;a write data buffer for storing plural data which are transmitted with use of said multiplex bus;a comparator for deciding whether there are continuous write addresses in the write addresses stored in said write buffer;a timer for measuring a predetermined time period after receipt of one access; andconverting means for converting accesses corresponding to writing operations of the plural write data stored in said write data buffer, corresponding to said continuous write addresses, into fixed length burst transfer protocol which can be transferred at a series of continuous data cycles following one address cycle, when said continuous write addresses are detected by said comparator, wherein said plural write data are transferred by the writing operations which are converted into said fixed length burst transfer protocol,wherein said comparator determines whether said one access and other accesses are continuous in the address thereof, when receiving said predetermined number of other accesses within said predetermined time period measured by said timer, andwherein said converting means outputs said accesses corresponding to write addresses stored in said buffer by converting said accesses into the fixed length burst transfer protocol when said one access and said predetermined number of other accesses are continuous in the address thereof.8. A processor for an information processing equipment, as defined in the claims 7, wherein said comparator decides whether the write addresses stored next to each other in said buffer are in succession or not.9. A processor for an information processing equipment, as defined in the claim 7, wherein said plural write data is transferred from said multiplex bus through a bus converter to a bus being different from said multiplex bus.10. A processor for an information processing equipment, as defined in the claim 7, further comprising means for initializing the transfer of write data with a delay of a predetermined time period when there are detected the continuing write addresses within said write address buffer with said comparator.11. A processor for an information processing equipment, as defined in the claim 10, further comprising means for setting up a value of said predetermined time period selectively.12. A processor for an information processing equipment, as defined in claim 7, wherein said processor is integrated on a single chip.13. A control method of a processor for an information processing equipment having a unit for executing calculation processes therein, wherein at least one of buses, being connected as an input/output means to an outside of said processor, is a multiplex bus with which address and data are used in a time-sharing man ner, said control method comprising: transferring by said processor data according to fixed length burst transfer protocol which can transfers data with a series of continuous data cycles following one address cycle;storing in a write address buffer plural sets of write addresses for said bus,storing in a write data plural sets of write data for said bus;deciding in a comparator whether access requirements, corresponding to write addresses, are continuous relative to each other in the write addresses thereof or not, within a predetermined time period after receipt of one access; andconverting plural access requirements corresponding to write operations for the continuous write addresses into fixed length burst transfer protocol which can be transferred as a series of continuing data cycles following one address cycle,wherein when detecting the access requirements relative to each other, being continuous in the write addresses thereof within the predetermined time period after receipt of the one access, the plural write operations for said continuous write addresses is converted into the fixed length burst transfer protocol which can be transferred at the series of continuing data cycles following the one address cycle.14. A processor for an information processing equipment, having an unit for executing calculation processes, comprising: a buffer which stores plural sets of write addresses for a system bus of said information processing equipment and plural data corresponding to said write addresses;a comparator for deciding whether there are write addresses in succession or not in the write addresses stored in said buffer;a timer for measuring a predetermined time period after receipt of one access; andconverting means for converting respective accesses corresponding to writing operations of the plural data, corresponding to said continuous write addresses in succession, into burst transfer protocol which can be transmitted with a series of continuing data cycles following one address cycle, when said continuous write addresses are detected by said comparator,wherein said comparator determines whether said one access and other access are continuous in the address thereof, when receiving said other access within said predetermined time period,wherein said converting means outputs said access corresponding to write addresses stored in said buffer by converting said accesses into the burst transfer protocol when said one access and said other access are continuous in the address thereof,wherein observation is made on whether a second access is made or not within said predetermined time period by initiating said timer, when a first access is made,wherein said first access is transmitted as a single access when said second access is not made within said predetermined time period,wherein determination is made on whether said first access and said second access are continuous or not in the write addresses thereof when said second access is made within said predetermined time period,wherein said first access is transmitted as a single access when said write addresses are not continuous, andwherein observation is made on presence of a third access within a predetermined time period by resetting said timer, and said first and second accesses are converted into the burst protocol, to be transmitted, when said third access is not made within said predetermined time period.15. A processor for an information processing equipment, executing calculation processes, being connected with a multiplex bus with which address and data are used in time-sharing manner, comprising: a write address buffer for storing plural write addresses which