초록 ▼

Family of methods for correcting errors in transfer of information over a lossy medium. The message to be sent is first broken into Data Blocks, which are further divided into N data segments. These data segments are sent verbatim and followed by XOR combinations of the data segments, called Error C

Family of methods for correcting errors in transfer of information over a lossy medium. The message to be sent is first broken into Data Blocks, which are further divided into N data segments. These data segments are sent verbatim and followed by XOR combinations of the data segments, called Error Correcting Segments. Incorrect Data or Error Correcting Segments are detected through the use of a CRC or any other error detection algorithm, and errored Data or Error Correcting Segments are discarded. Once all Data or Error Correcting Segments for a message segment are received, logic or a look up table is used to determine which of the Data Segments can be recovered. The lost Data Segment recovery is done using a binary XOR of multiple good Data or Error Correcting Segments. For additional error correction, Data and Error Correcting Segments can also be repeatedly transmitted multiple times to further improve the performance of this algorithm.

대표청구항 ▼

Family of methods for correcting errors in transfer of information over a lossy medium. The message to be sent is first broken into Data Blocks, which are further divided into N data segments. These data segments are sent verbatim and followed by XOR combinations of the data segments, called Error C

Family of methods for correcting errors in transfer of information over a lossy medium. The message to be sent is first broken into Data Blocks, which are further divided into N data segments. These data segments are sent verbatim and followed by XOR combinations of the data segments, called Error Correcting Segments. Incorrect Data or Error Correcting Segments are detected through the use of a CRC or any other error detection algorithm, and errored Data or Error Correcting Segments are discarded. Once all Data or Error Correcting Segments for a message segment are received, logic or a look up table is used to determine which of the Data Segments can be recovered. The lost Data Segment recovery is done using a binary XOR of multiple good Data or Error Correcting Segments. For additional error correction, Data and Error Correcting Segments can also be repeatedly transmitted multiple times to further improve the performance of this algorithm. eans for dividing all the logic paths through a logic gate into two groups based oh whether signal transit time of their path from a launch latch to a capture latch is faster or slower than a threshold level;(b) means for performing simulation testing by shifting a plurality of pseudo random pulse patterns through said paths to detect faults on fault lists for the paths;(c) means for determining if a fault occurred during simulation testing in paths with transit times longer than the threshold level and checking off of the fault from the fault list;(d) means for checking for a longer path above the threshold with faults unexercised by the simulation testing; ande) means for generating a test for the longer path for forcing an untested fault through the longer path.8. The apparatus of claim 7 including means for treating the paths in either group as a single path.9. The apparatus of claim 7, further comprising:(f) means for treating all paths in the group containing the shorter transit times as tested when the threshold is exceeded in the simulation testing (b); and(g) means for treating all paths in the group containing the longer path as tested when the longest path in that group has been tested by the means of determining.10. The apparatus of claim 9 including means for not marking off faults detected in path with a transit time shorter than the threshold.11. The apparatus of claim 10 including means for marking off a detected fault in the longest path in which it is detected.12. A method of testing a combinational and sequential logic circuit including a plurality of logic units coupled to form a shift register scan path for testing the logic circuit and being configured to uncouple to disable the scan path while the logic circuit is performing a designed logic function, comprising the steps of: (a) dividing all the logic paths through a logic gate into two groups based on whether signal transit time of their path from a launch latch to a capture latch is faster or slower than a threshold level, the threshold value being based on an accepted pulse rest time relative to the longest path;(b) performing simulation testing by shifting a plurality of pseudo random pulse patterns through said paths to detect faults on fault lists for the paths;(c) determining if a fault occurred during simulation testing in paths with transit times longer than the threshold level and checking off of the fault from the fault list;(d) checking for a longer path above the threshold with faults unexercised by the simulation testing;(e) generating a test for the longer path for forcing an untested fault through the longer path;(f) treating all paths in the group containing the shorter transit times as tested when the threshold is exceeded in simulation test of step (b); and(g) treating all paths in the group containing the longer path as tested when the longest path in that group has been tested using the test generated in step (c).13. The method of claim 12, further including not marking off faults detected in path with a transit time shorter than the threshold.14. The method of claim 13 including the step of marking of a detected fault in the longest path in which the detected fault is detected.15. The method of claim 12, further including generating testing sequences for self-testing the logic circuit.16. The method of claim 12, further including compressing responses from the logic circuit.