Process for testing a xenon gas feed system of a hollow cathode assembly
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G01M-003/26
G01M-003/28
G01N-037/00
출원번호
US-0216679
(2002-08-08)
발명자
/ 주소
Patterson, Michael J.
Verhey, Timothy R. R.
Soulas, George C.
출원인 / 주소
The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
대리인 / 주소
Stone, Kent N.
인용정보
피인용 횟수 :
1인용 특허 :
12
초록▼
The design and manufacturing processes for Hollow Cathode Assemblies (HCA's) that operate over a broad range of emission currents up to 30 Amperes, at low potentials, with lifetimes in excess of 17,500 hours. The processes include contamination control procedures which cover hollow cathode component
The design and manufacturing processes for Hollow Cathode Assemblies (HCA's) that operate over a broad range of emission currents up to 30 Amperes, at low potentials, with lifetimes in excess of 17,500 hours. The processes include contamination control procedures which cover hollow cathode component cleaning procedures, gas feed system designs and specifications, and hollow cathode activation and operating procedures to thereby produce cathode assemblies that have demonstrated stable and repeatable operating conditions, for both the discharge current and voltage. The HCA of this invention provides lifetimes of greater than 10,000 hours, and expected lifetimes of greater than 17,500 hours, whereas the present state-of-the-art is less than 500 hours at emission currents in excess of 1 Ampere. Stable operation is provided over a large range of operating emission currents, up to a 6:1 ratio, and this HCA can emit electron currents of up to 30 Amperes in magnitude to an external anode that simulates the current drawn to a space plasma, at voltages of less than 20 Volts.
대표청구항▼
The design and manufacturing processes for Hollow Cathode Assemblies (HCA's) that operate over a broad range of emission currents up to 30 Amperes, at low potentials, with lifetimes in excess of 17,500 hours. The processes include contamination control procedures which cover hollow cathode component
The design and manufacturing processes for Hollow Cathode Assemblies (HCA's) that operate over a broad range of emission currents up to 30 Amperes, at low potentials, with lifetimes in excess of 17,500 hours. The processes include contamination control procedures which cover hollow cathode component cleaning procedures, gas feed system designs and specifications, and hollow cathode activation and operating procedures to thereby produce cathode assemblies that have demonstrated stable and repeatable operating conditions, for both the discharge current and voltage. The HCA of this invention provides lifetimes of greater than 10,000 hours, and expected lifetimes of greater than 17,500 hours, whereas the present state-of-the-art is less than 500 hours at emission currents in excess of 1 Ampere. Stable operation is provided over a large range of operating emission currents, up to a 6:1 ratio, and this HCA can emit electron currents of up to 30 Amperes in magnitude to an external anode that simulates the current drawn to a space plasma, at voltages of less than 20 Volts. a total number of Logic 1 bits in said group of N data bits. 7. The circuit for determining the number of Logic 1 bits as set forth in claim 6 wherein N equals 16 and said input stage comprises three 6:3 carry-save adders.8. The circuit for determining the number of Logic 1 bits as set forth in claim 7 wherein said intermediate stage comprises three 4:2 carry-save adders.9. The circuit for determining the number of Logic 1 bits as set forth in claim 6 wherein N equals 32 and said input stage comprises six 6:3 carry-save adders.10. The circuit for determining the number of Logic 1 bits as set forth in claim 9 further comprising a second intermediate stage of 4:2 carry-save adders, each of said second intermediate stage 4:2 carry-save adders having four input lines for receiving selected ones of said COUT bits, said C-bits, and said S-bits from said first intermediate stage 4:2 carry-save adders.11. A circuit for determining the number of Logic 1 bits in a group of N data bits comprising: an input stage of 8:4 carry-save adders, each of said 8:4 carry-save adders receiving eight of said N data bits on eight input lines and generating four sum bits (S 3, S2, S1, S0) equal to a total number of Logic 1 bits on said eight input lines, wherein said four sum bits have bit weights of S3=8, S2=4, S1=2 and S0=4, respectively; a first intermediate stage of 4.2 carry-save adders, each of said first intermediate stage 4.2 carry-save adders having four input lines for receiving selected ones of said S 3 sum bits, said S2 sum bits, said S1 sum bits, and said S0 sum bits and generating therefrom a carry-out (COUT) bit, a carry (C) bit and a sum (S) bit; and a carry-propagate adder having a first input channel and a second input channel coupled to said first intermediate stage 4:2 carry-save adders and capable of generating a binary result equal to a total number of Logic 1 bits in said group of N data bits. 12. The circuit for determining the number of Logic 1 bits as set forth in claim 11 wherein N equals 16 and said input stage comprises two 8:4 carry-save adders.13. The circuit for determining the number of Logic 1 bits as set forth in claim 12 wherein said intermediate stage comprises two 4:2 carry-save adders.14. The circuit for determining the number of Logic 1 bits as set forth in claim 11 wherein N equals 32 and said input stage comprises four 8:4 carry-save adders.15. The circuit for determining the number of Logic 1 bits as set forth in claim 14 comprising a second intermediate stage of 4:2 carry-save adders, each of said second intermediate stage 4:2 carry-save adders having four input lines for receiving selected ones of said COUT bits, said C-bits, and said S-bits from said first intermediate stage 4:2 carry-save adders.16. A data processor comprising: an instruction execution pipeline comprising N processing stages, each of said N processing stages capable of performing one of a plurality of execution steps associated with a pending instruction being executed by said instruction execution pipeline, wherein at least one of said N processing stages comprises a counting circuit for determining the number of Logic 1 bits in one of a N-bit data bus and a N-bit register in said data processor, said counting circuit comprising: an input stage of 4:3 carry-save adders, each of said 4.3 carry-save adders receiving four of said N data bits on four input lines and generating three sum bits (S2, S1, S0) equal to a total number of Logic 1 bits on said four input lines, wherein said three sum bits have bit weights of S2=4, S1=2 and S0=1, respectively;a first intermediate stage of 4:2 carry-save adders, each of said first intermediate stage 4:2 carry-save adders having four input lines for receiving selected ones of said S2 sum bits, said S1 sum bits, and said S0 sum bits and generating therefrom a carry-out (COUT) bit, a carry (C) bit and a sum (S) bit; anda carry-propagate adder having a first input channel and a second input chan
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이 특허에 인용된 특허 (12)
Williamson Weldon S. (Malibu CA), Compact penning-discharge plasma source.
Gavrilov Nikolai V. (Cherepanova St. 24 ; Apt. 229 620034 Ekaterinberg RUX) Nikulin Sergey P. (Vikoolova 43 ; Bldg. 3 ; Apt. 80 620131 Ekaterinburg RUX), Ion emmiter based on cold cathode discharge.
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