$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

[미국특허] Semiconductor integrated circuit device with vertically stacked conductor interconnections 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/52
  • H01L-029/40
출원번호 US-0613138 (2000-07-10)
우선권정보 JP-0234236 (1997-08-29); JP-0182813 (1998-06-29)
발명자 / 주소
  • Saito, Tatsuyuki
  • Noguchi, Junji
  • Yamaguchi, Hizuru
  • Owada, Nobuo
출원인 / 주소
  • Hitachi, Ltd.
대리인 / 주소
    Antonelli, Terry, Stout & Kraus, LLP
인용정보 피인용 횟수 : 31  인용 특허 : 15

초록

In a semiconductor integrated circuit device, upon connection of an interconnection made of aluminum or aluminum alloy and another interconnection made of Cu or Cu alloy, a barrier conductor film or plug is disposed at the joint portion between these interconnections. Among the interconnection layer

대표청구항

In a semiconductor integrated circuit device, upon connection of an interconnection made of aluminum or aluminum alloy and another interconnection made of Cu or Cu alloy, a barrier conductor film or plug is disposed at the joint portion between these interconnections. Among the interconnection layer

이 특허에 인용된 특허 (15) 인용/피인용 타임라인 분석

  1. Chan Lap ; Zheng Jia Zhen,SGX, Copper interconnect with top barrier layer.
  2. Edelstein Daniel Charles ; Harper James McKell Edwin ; Hu Chao-Kun ; Simon Andrew H. ; Uzoh Cyprian Emeka, Copper interconnection structure incorporating a metal seed layer.
  3. Wollesen Donald L. (Saratoga CA), High conductivity interconnection line.
  4. Colgan Evan G. (Suffern NY) Rodbell Kenneth P. (Poughguag NY) Totta Paul A. (Poughkeepsie NY) White James F. (Newburgh NY), Interconnect structure using a Al2Cu for an integrated circuit chip.
  5. Chung Henry Wei-Ming (Cupertino CA), Interconnect structures for integrated circuits.
  6. Tabara Suguru,JPX, Interconnection with metal plug and reduced step.
  7. Grill Alfred ; Jahnes Christopher Vincent ; Patel Vishnubhai Vitthalbhai ; Saenger Katherine Lynn, Method and material for integration of fuorine-containing low-k dielectrics.
  8. Chiang Chien ; Fraser David B., Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections.
  9. Schilling ; Hartmut, Multilayer interconnected structure for semiconductor integrated circuit.
  10. Thomas David C. (Wilkes-Barre PA) Wong S. Simon (Ithaca NY), Planar tungsten interconnect with implanted silicon.
  11. Matsumoto Hiroshi (Hyogo JPX), Semiconductor device in which wiring layer is formed below bonding pad.
  12. Oku Kazutoshi (Hyogo JPX) Hirosue Masahiro (Hyogo JPX), Semiconductor device with an elevated bonding pad.
  13. Isono Toshio (Tokyo JPX), Semiconductor integrated circuit device having an electrode pad including an extended wire bonding portion.
  14. Cabral ; Jr. Cyril ; DeHaven Patrick William ; Edelstein Daniel Charles ; Klaus David Peter ; Pollard ; III James Manley ; Stanis Carol L. ; Uzoh Cyprian Emeka, Thin metal barrier for electrical interconnections.
  15. Sardella John C., Vias and contact plugs with an aspect ratio lower than the aspect ratio of the structure in which they are formed.

이 특허를 인용한 특허 (31) 인용/피인용 타임라인 분석

  1. Fishburn, Fred, Contact structure.
  2. Kuhn, Kelin J.; Mistry, Kaizad; Bohr, Mark; Auth, Chris, Copper-filled trench contact for transistor performance improvement.
  3. Kuhn, Kelin J.; Mistry, Kaizad; Bohr, Mark; Auth, Chris, Copper-filled trench contact for transistor performance improvement.
  4. Righter,Alan W, Integrated circuit bond pad structures and methods of making.
  5. Righter,Alan W., Integrated circuit bond pad structures and methods of making.
  6. Zhai, Jun; Wang, Fei, Interconnects with improved electromigration reliability.
  7. Zhai, Jun; Wang, Fei, Interconnects with improved electromigration reliability.
  8. Wu,Zhen Cheng; Jang,Syun Ming, Metal barrier integrity via use of a novel two step PVD-ALD deposition procedure.
  9. Ha,Jo Woong; Kim,Seung Hyun; Park,Dong Yeon; Lee,Dong Su; Woo,Hyun Jung, Method for manufacturing metal thin film resistor.
  10. Fishburn,Fred, Method of forming a contact structure including a vertical barrier structure and two barrier layers.
  11. Jang, Jae Hoon; Jung, Soon Moon; Kwak, Kun Ho; Hwang, Byung Jun, Node contact structures in semiconductor devices.
  12. Wang, Kun-Chih; Wu, Bing-Chang, Semiconductor chip capable of implementing wire bonding over active circuits.
  13. Wang,Kun Chih; Wu,Bing Chang, Semiconductor chip capable of implementing wire bonding over active circuits.
  14. Hatano,Keisuke; Abiru,Takahisa, Semiconductor device.
  15. Hayashi, Masahiro; Akiba, Takahisa; Watanabe, Kunio; Takaso, Tomo; Kenmochi, Susumu, Semiconductor device.
  16. Yamada, Masaki, Semiconductor device and fabrication method for the same.
  17. Yamada, Masaki, Semiconductor device and fabrication method for the same.
  18. Lee, Chanho; Chung, Hyunsoo; Ryu, Hansung; Lee, InYoung, Semiconductor device and method for manufacturing the same.
  19. Lin, Li-Jen; Murphy, Stephen A.; Sun, Wei, Semiconductor device and method of forming a dual UBM structure for lead free bump connections.
  20. Park, Sung Kee, Semiconductor device having pad structure for preventing and buffering stress of silicon nitride film.
  21. Park,Sun Kee, Semiconductor device having pad structure for preventing and buffering stress of silicon nitride film.
  22. Suzuki,Takehiro, Semiconductor device using inorganic film between wiring layer and bonding pad.
  23. Oda, Noriaki, Semiconductor device with bonding pad support structure.
  24. Oda,Noriaki, Semiconductor device with bonding pad support structure.
  25. Lee, Ho-Jin; Park, Byunglyul; Park, Jisoon; An, Jinho, Semiconductor devices having a TSV, a front-side bumping pad, and a back-side bumping pad.
  26. Maeda, Jun, Semiconductor integrated circuit having connection pads over active elements.
  27. Yang, Chih-Chao; Cohen, Stephen A; Li, Baozhen, Semiconductor switching device and method of making the same.
  28. Lee, Ki-Don; Kim, Jinseok, Stacked damascene structures for microelectronic devices.
  29. Lee, Ho-Jin; Kang, Pil-Kyu; Lee, Kyu-Ha; Park, Byung-Lyul; Chung, Hyun-Soo; Choi, Gil-Heyun, Via connection structures, semiconductor devices having the same, and methods of fabricating the structures and devices.
  30. Yamamoto,Hiroshi, Wiring structure of a semiconductor integrated circuit and a method of forming the wiring structure.
  31. Matsunaga, Noriaki; Usui, Takamasa; Ito, Sachiyo, Wiring structure of semiconductor device.

활용도 분석정보

상세보기
다운로드
내보내기

활용도 Top5 특허

해당 특허가 속한 카테고리에서 활용도가 높은 상위 5개 콘텐츠를 보여줍니다.
더보기 버튼을 클릭하시면 더 많은 관련자료를 살펴볼 수 있습니다.

섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로