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Complement reset multiplexer latch 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-017/00
출원번호 US-0421991 (2003-04-22)
발명자 / 주소
  • Masleid, Robert P.
  • Harada, Akihiko
  • Giacomotto, Christophe
출원인 / 주소
  • Fujitsu Limited
대리인 / 주소
    Fenwick & West LLP
인용정보 피인용 횟수 : 51  인용 특허 : 15

초록

A complement reset multiplexer latch is provided. The complement reset multiplexer latch selectively regenerates a first or a second data input signal on an output node. To react to rising edges of the first or the second data signal, the complement reset multiplexer latch includes a first and a sec

대표청구항

A complement reset multiplexer latch is provided. The complement reset multiplexer latch selectively regenerates a first or a second data input signal on an output node. To react to rising edges of the first or the second data signal, the complement reset multiplexer latch includes a first and a sec

이 특허에 인용된 특허 (15)

  1. Stark Donald C. ; Sidiropoulos Stefanos, Apparatus and method for edge based duty cycle conversion.
  2. Jeddeloh Joseph M., Apparatus for aligning clock and data signals received from a RAM.
  3. Vincenzo DiTommaso, Buffer circuit with rising and falling edge propagation delay correction and method.
  4. Masleid Robert Paul (Austin TX) Phillips Larry Bryce (Austin TX), Clock distribution network for reducing clock skew.
  5. Eiji Komoto JP, Clock signal switching circuit.
  6. David J. Greenhill ; Pradeep Trivedi, Dual-edge triggered dynamic logic.
  7. Masleid Robert Paul, Gain enhanced split drive buffer.
  8. David W. Boerstler ; Gary D. Carpenter ; Hung C. Ngo ; Kevin J. Nowka, Glitch-less clock selector.
  9. Masleid Robert P. (Austin TX), Independent clock edge regulation.
  10. Merritt Todd A., Multiplexed semiconductor data transfer arrangement with timing signal generator.
  11. Chung-Hui Chen TW, Push-pull output buffer with gate voltage feedback loop.
  12. Alan Lloyd GB, Selective modification of clock pulses.
  13. Proebsting Robert J., Separate set/reset paths for time critical signals.
  14. Masleid Robert P. (Austin TX), Split drive clock buffer.
  15. Galambos Tiberiu Carol,ILX ; Masleid Robert Paul ; Wagner Israel Abraham,ILX, System and method for robust clocking schemes for logic circuits.

이 특허를 인용한 특허 (51)

  1. Pitkethly, Scott; Masleid, Robert Paul, Advanced repeater utilizing signal distribution delay.
  2. Pitkethly,Scott; Masleid,Robert Paul, Advanced repeater utilizing signal distribution delay.
  3. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  4. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  5. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  6. Pitkethly,Scott, Advanced repeater with duty cycle adjustment.
  7. Masleid, Robert Paul; Dholabhai, Vatsal, Circuit with enhanced mode and normal mode.
  8. Masleid, Robert Paul; Kowalczyk, Andre, Circuits and methods for detecting and assisting wire transitions.
  9. Masleid,Robert Paul; Kowalczyk,Andre, Circuits and methods for detecting and assisting wire transitions.
  10. Masleid,Robert Paul; Kowalczyk,Andre, Circuits and methods for detecting and assisting wire transitions.
  11. Masleid, Robert, Circuits, systems and methods relating to a dynamic dual domino ring oscillator.
  12. Masleid,Robert P., Circuits, systems and methods relating to dynamic ring oscillators.
  13. Masleid, Robert Paul, Column select multiplexer circuit for a domino random access memory array.
  14. Masleid, Robert Paul, Configurable delay chain with stacked inverter delay elements.
  15. Masleid,Robert Paul, Configurable delay chain with stacked inverter delay elements.
  16. Masleid, Robert Paul, Configurable delay chain with switching control for tail delay elements.
  17. Masleid, Robert Paul, Configurable tapered delay chain with multiple sizes of delay elements.
  18. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  19. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  20. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  21. Masleid, Robert P, Dynamic ring oscillators.
  22. Masleid,Robert Paul, Elastic pipeline latch with a safe mode.
  23. Masleid, Robert P, Inverting zipper repeater circuit.
  24. Masleid, Robert P., Inverting zipper repeater circuit.
  25. Masleid, Robert Paul, Inverting zipper repeater circuit.
  26. Masleid,Robert P., Inverting zipper repeater circuit.
  27. Masleid, Robert, Leakage efficient anti-glitch filter.
  28. Masleid,Robert Paul, Leakage efficient anti-glitch filter with variable delay stages.
  29. Rozas, Guillermo J.; Masleid, Robert P., Method and system for elastic signal pipelining.
  30. Lablans, Peter, Multi-state latches from n-state reversible inverters.
  31. Masleid, Robert Paul, Power efficient multiplexer.
  32. Masleid, Robert Paul, Power efficient multiplexer.
  33. Masleid, Robert Paul, Power efficient multiplexer.
  34. Masleid, Robert Paul, Power efficient multiplexer.
  35. Masleid,Robert Paul, Power efficient multiplexer.
  36. Masleid, Robert Paul; Dholabhai, Vatsal; Klingner, Christian, Repeater circuit having different operating and reset voltage ranges, and methods thereof.
  37. Masleid,Robert Paul; Dholabhai,Vatsal; Klingner,Christian, Repeater circuit having different operating and reset voltage ranges, and methods thereof.
  38. Masleid,Robert Paul; Dholabhai,Vatsal; Stoiber,Steven Thomas; Singh,Gurmeet, Repeater circuit with high performance repeater mode and normal repeater mode.
  39. Masleid, Robert Paul; Dholabhai, Vatsal, Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability.
  40. Masleid,Robert Paul; Dholabhai,Vatsal, Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability.
  41. Masleid, Robert P.; Dixit, Anand, Repeater circuit with multiplexer and state element functionality.
  42. Stoiber, Steven T.; Siu, Stuart, Ring based impedance control of an output driver.
  43. Stoiber, Steven T.; Siu, Stuart, Ring based impedance control of an output driver.
  44. Maliuk, Dzmitry S.; Stellari, Franco; Weger, Alan J.; Song, Peilin, Scan chain latch design that improves testability of integrated circuits.
  45. Maliuk, Dzmitry S.; Stellari, Franco; Weger, Alan J.; Song, Peilin, Scan chain latch design that improves testability of integrated circuits.
  46. Masleid, Robert Paul; Sousa, Jose; Kottapalli, Venkata, Scannable dynamic circuit latch.
  47. Masleid, Robert P.; Burr, James B., Stacked inverter delay chain.
  48. Masleid,Robert P.; Burr,James B., Stacked inverter delay chain.
  49. Bogenberger, Florian; Reipold, Anthony; Sakada, Oleksandr, Synchronization of stateful elements in a processing resource using a scan chain.
  50. Pitkethly, Scott; Masleid, Robert P., Triple latch flip flop system and method.
  51. Pitkethly,Scott; Masleid,Robert P., Triple latch flip flop system and method.
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