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A CDMA system in which the base stations transmit a synchronization channel comprising a primary subchannel from which slot synchronization is determinate and a secondary subchannel containing a cyclic hierarchical code unique for each base station and for each slot in a frame. The cyclic code is de

A CDMA system in which the base stations transmit a synchronization channel comprising a primary subchannel from which slot synchronization is determinate and a secondary subchannel containing a cyclic hierarchical code unique for each base station and for each slot in a frame. The cyclic code is derived from a first code unique to a base station and a different cyclic shift of a second code also unique to the base station in each slot of a frame. Mobile stations quickly and with low-complexity detectors determine slot synchronization from the primary subchannel and then determine base station identification and frame synchronization by correlating samples of signal received on the secondary subchannel with a set of first codes and cyclic shifts of corresponding second codes.

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A CDMA system in which the base stations transmit a synchronization channel comprising a primary subchannel from which slot synchronization is determinate and a secondary subchannel containing a cyclic hierarchical code unique for each base station and for each slot in a frame. The cyclic code is de

A CDMA system in which the base stations transmit a synchronization channel comprising a primary subchannel from which slot synchronization is determinate and a secondary subchannel containing a cyclic hierarchical code unique for each base station and for each slot in a frame. The cyclic code is derived from a first code unique to a base station and a different cyclic shift of a second code also unique to the base station in each slot of a frame. Mobile stations quickly and with low-complexity detectors determine slot synchronization from the primary subchannel and then determine base station identification and frame synchronization by correlating samples of signal received on the secondary subchannel with a set of first codes and cyclic shifts of corresponding second codes. gister having n storage elements, where n is a natural number except 1, the method comprising: outputting in parallel n data bits corresponding to n data pieces held in each of the n storage elements of the bit circulative shift register in a first state, from a storage; multiplying each data bit corresponding to each data piece held in each storage element of the bit circulative shift register in the first state by a vector operation coefficient for n-step shifting to generate n data bits corresponding to each data piece held in each storage element of the bit circulative shift register to form a second state, and outputting each data piece obtained as the result of the multiplying operation in parallel from the storage; and multiplying each data bit corresponding to each data piece held in each storage element of the bit circulative shift register in the second state by a vector operation coefficient for n-step shifting to generate n data bits corresponding to each data piece held in each storage element of the bit circulative shift register to form a third state, and outputting each data piece obtained as a result of the multiplication in parallel from the storage circuit. 5. A spreading code generator using vector operations to perform processing substantially equivalent to generation, with a bit circulative shift register, of M-sequence spreading codes expressed by a predetermined generator polynomial, said bit circulative shift register having n storage elements, where n is a natural number except 1, said spreading code generator comprising; a register, having n storage elements that enable n data bits to be input thereto and output therefrom in parallel; an initial value generator that generates an initial value of said register and outputs generated n data bits in parallel; a vector multiplier that multiplies each of the n data bits output in parallel from said register by a vector operation coefficient that imparts to each bit an amount of shift corresponding to n bits in said bit circulative shift register, and that outputs n data bits obtained as a result of multiplication in parallel; and a selector that selects one of a parallel output of n bits from said vector multiplier and a parallel output of n bits from said initial value generator to input to said register. 6. The spreading code generator according to claim 5, wherein said initial value generator includes: a register having n storage elements that enable n data bits to be input thereto and output therefrom in parallel; a vector multiplier that multiplies each bit of n data bits output in parallel from said register by a vector operation coefficient that imparts an amount of shift corresponding to the number of bits in said bit circulative shift register, and that outputs n data bits obtained as a result of said multiplication in parallel; and a selector that selects one of a parallel output of n bits from said vector multiplier and an externally input initial data comprising of n bits to input to said register. 7. The spreading code generator according to claim 5, wherein said initial value generator includes: a first register having k storage elements, where k is a natural number except 1, and capable of parallel input and output of k-bit data; a vector operation coefficient generator that generates one of a first vector operation coefficient that provides predetermined amount of shift corresponding to a number of bits of said bit circulative shift register and a second vector operation coefficient that provides certain amount of shift required for bit extension of an M-sequence initial value; a vector multiplier that multiplies each of k-bit data output in parallel from said first register by one of said first vector operation coefficient and by said second vector operation coefficient, to provide as parallel output k-bit data obtained as a result of said multiplication; a selector that selects one of a k-bit paralle l output from said vector multiplier as a result of said multiplication of said first vector operation coefficient and an externally input k-bit initial data, said selector providing a selected one of the k-bit parallel output and k-bit initial data as its parallel output to said first register; and a second register that stores at least a part of k-bit data output in parallel from said vector multiplier as a result of said multiplication of said second vector operation coefficient, said second register serving to output in parallel at least a part of said stored data as M-sequence initial value extension bits, wherein data bits output in parallel from said first register and from said second register are summed to obtain an M-sequence initial value. 8. A spreading code generator using vector operations to perform processing substantially equivalent to generation, with a bit circulative shift register, of M-sequence spreading codes expressed by a predetermined generator polynomial, said bit circulative shift register having n storage elements, where n is a natural number except 1, said spreading code generator comprising: a register having n storage elements and capable of parallel input and output of n-bit data; an initial value generator that generates an initial value of said register and that provides as parallel output generated n-bit data; a vector operation coefficient generator that generates one of a first vector operation coefficient that provides a certain amount of shift corresponding to n bits of said bit circulative shift register and a second vector operation coefficient that provides an amount of shift corresponding to the number of bits from the terminal end of one M-sequence spreading code up to the initial value of M-sequence spreading code to next be generated; a vector multiplier that multiplies each of n-bit data output in parallel from said register by one of said first and second vector operation coefficient, to output in parallel n-bit data obtained as a result of said multiplication; and a selector that selects one of an n-bit parallel output of said vector multiplier and an n-bit parallel output of said initial value generator, said selector capable of providing a selected one output as its parallel output to said register. 9. A spreading code generator using vector operations to perform processing substantially equivalent to generation, with a bit circulative shift register, of M-sequence spreading codes expressed by a predetermined generator polynomial, said bit circulative shift register having n storage elements where n is a natural number except 1, said spreading code generator comprising: a register having n storage elements and capable of parallel input and output of n-bit data; a vector operation coefficient generator that generates one of a first vector operation coefficient that provides the amount of shift corresponding to n bits of said bit circulative shift register and a second vector operation coefficient that provides a shift required for generation of data corresponding to an initial value of said bit circulative shift register; a vector multiplier that multiplies each of n-bit data output in parallel from said register by one of said first vector operation coefficient and by said second vector operation coefficient, to provide as parallel output n-bit data obtained as a result of said multiplication; and a selector that selects one of a n-bit parallel output of said vector multiplier and a reference value required for generation of data corresponding to said initial value of said bit circulative shift register, said register capable of providing selected one of the n-bit parallel output and the reference value as its output to said register. 10. A spreading code generator using vector operations to perform processing substantially equivalent to generation, with a bit circulative shift register, of M-sequence spreading codes expressed by a predetermi ned generator polynomial, said bit circulative shift register having n storage elements, where n is a natural number except 1, said spreading code generator comprising: a register having n storage elements and capable of parallel input and output of n data bits; a vector operation coefficient generator that generates one of a first vector operation coefficient that provides an amount of shift corresponding to n bits of said bit circulative shift register and a second vector operation coefficient that provides a shift required for generation of data corresponding to an initial value of said bit circulative shift register; a first vector multiplier that multiplies each of n bit data bits output in parallel from said register by one of said first vector operation coefficient and by said second vector operation coefficient, to output in parallel each of n data bits resulting from said multiplication as spreading codes for quadrature components of quadrature modulation signals or for in-phase components thereof; a selector that selects one of n data bits output in parallel from said first vector multiplier and a reference value required for generation of data corresponding to said initial value of said bit circulative shift register, said selector capable of providing selected one of the n data bits output and the reference value as its output to said register; and a second vector multiplier that multiplies each of n-bit parallel output data from said register by a vector operation coefficient, to thereby acquire n data bits whose phase has been shifted by a desired number of bits, said second vector multiplier outputs in parallel the resultant n data bits as spreading codes for in-phase components of one of quadrature modulation signals and for quadrature components thereof. 11. A spreading code generator using vector operations to perform processing substantially equivalent to generation, with a bit circulative shift register, of M-sequence spreading codes expressed by a predetermined generator polynomial, said bit circulative shift register having n storage elements, where n is a natural number except 1, said spreading code generator comprising: a plurality of registers each having n storage elements and each capable of parallel input and output of n data bits; a selector that selects n data bits output in parallel from one of a plurality of registers; a vector operation coefficient generator that generates one of a first vector operation coefficient that provides the amount of shift corresponding to n bits of said bit circulative shift register and a second vector operation coefficient that provides a shift required for generation of data corresponding to an initial value of said bit circulative shift register; a vector multiplier that multiplies each of n-bit data output in parallel from said selector by one of said first vector operation coefficient and by said second vector operation coefficient, said vector multiplier providing as its parallel output n-bit data obtained as a result of said multiplication; and a selector that selects one of n bits data output in parallel from said vector multiplier and a reference value required for generation of data corresponding to said initial value of said bit circulative shift register, said selector capable of providing the selected one of the n bits data output and the reference value as its output to each of said plurality of registers. 12. A correlation detector comprising: a spreading code generator as recited in claim 5; a correlation detector; and a RAM that temporarily stores received spreading modulation signals; wherein said correction detector latches said spreading modulation signals stored in said RAM, and said spreading code generator generates different spreading codes in a successive manner, said spreading modulation signals latched in said correction detector being multiplied by said different spreading codes to thereby detect co rrelations. 13. A spreading spectrum signal receiving apparatus comprising: a correlation detector as recited in claim 12.14. A mobile communication terminal apparatus making use of a correlation detector as recited in claim 12 to acquire a synchronism of spreading spectrum modulation signals.15. A mobile communication system making use of a mobile communication terminal apparatus as recited in claim 14 to provide a communication control.16. A spreading code generator comprising: an M-sequence generator; a bit-width varier that varies the bit width of an output of said M-sequence generator; a register that allows parallel input and output and that temporarily stores spreading codes; a vector operation coefficient output that provides, as its output, a vector operation coefficient that provides the amount of shift for successive output of said spreading codes based on vector operations; a vector operator that multiplies output of said register by said vector operation coefficient; and a selector that allows a selective output of one of an output of said bit-width varier and an output of said vector operator. 17. A spreading code generator comprising: a register that temporarily stores spreading codes; a first vector operation coefficient output that provides as its output a first vector operation coefficient that imparts a phase shift by the amount of shift externally specified to an externally input M-sequence spreading code reference value; a second vector operation coefficient output that provides as its output a second vector operation coefficient that provides the amount of shift for successive output of M-sequence spreading codes based on vector operations; a vector operator that multiplies an output of said register by one of said first vector operation coefficient and by said second vector operation coefficient; and a selector that allows a selective output of one of an external input data and an output of said vector operation circuit. 18. A spreading code generator comprising: a register that temporarily stores M-sequence spreading codes; a first vector operation coefficient storage that stores a first vector operation coefficient externally specified that imparts a predetermined amount of phase shift to an M-sequence spreading code reference value; a second vector operation coefficient storage that stores a second vector operation coefficient externally specified that provides a shift required for successive output of M-sequence spreading codes based on vector operations; a vector operator that multiplies output of said register by said first vector operation coefficient or by said second vector operation coefficient; and a selector that allows a selective output of either externally input data or output of said vector operation circuit. 19. A spreading code generator comprising: a register that for temporarily stores M-sequence spreading codes; a first vector operation coefficient output that provides as its output a first vector operation coefficient that imparts a phase shift by the amount of shift externally specified to an M-sequence spreading code reference value; a second vector operation coefficient output that provides as its output a second vector operation coefficient that provides a phase shift required for successive output of M-sequence spreading codes based on vector operations; a first vector operator that multiplies output of said register by said first vector operation coefficient or by said second vector operation coefficient; a selector that allows a selective output of either external input or output of said first vector operation circuit; a third vector operation coefficient output that provides as its output a third vector operation coefficient that imparts a phase shift by the amount of shift externally specified to output of said register; and a second vector operator that makes vector operations of both output of said th ird vector operation coefficient output circuit and output of said register, said second vector operator provides as its output the results of vector operations; wherein said spreading code generator provides simultaneous parallel output of two series of M-sequence spreading codes having a phase difference externally specified. 20. A spreading code generator comprising: a plurality of spreading code storages; a spreading code selector that makes a selection of any one of outputs of said plurality of spreading code storages; a first vector operation coefficient output that provides, as its output, a first vector operation coefficient that imparts a phase shift by the amount of shift externally specified to a reference value of M-sequence spreading codes; a second vector operation coefficient output that provides as its output a second vector operation coefficient that provides a phase shift required for successive output of said M-sequence spreading codes based on vector operations; a vector operation coefficient selector that allows a selective output of one of an output of said first vector operation coefficient output and an output of said second vector operation coefficient output; a vector operator that multiplies spreading codes selected by said spreading code selector, by a vector operation coefficient selected by said vector operation coefficient selector; and a plurality of storage data selectors that each allow a selective output of any one of output of each of said plurality of spreading code storage, output of said vector operator, and externally input data; wherein said spreading code generator executes operations while switching in time-sharing mode respective outputs of said spreading code selector and of said vector operation coefficient selector, to thereby issue spreading codes in different operational conditions on a time-sharing basis.