초록 ▼

A method of forming an insulating material for use in an integrated circuit includes providing a substrate of the integrated circuit and forming a polymeric material on the substrate. At least a portion of the polymeric material is converted to a foamed polymeric material. The converting of the poly

A method of forming an insulating material for use in an integrated circuit includes providing a substrate of the integrated circuit and forming a polymeric material on the substrate. At least a portion of the polymeric material is converted to a foamed polymeric material. The converting of the polymeric material includes exposing at least a portion of the polymeric material to a supercritical fluid. Further, an integrated circuit includes a substrate of the integrated circuit and a foamed polymeric material on at least a portion of the substrate. The integrated circuit may further include a conductive layer adjacent the foamed polymeric material. The conductive layer may be a metal line on the foamed polymeric material, or the conductive layer may be an interconnect, e.g., a contact or a via, adjacent the foamed polymeric material.

대표청구항 ▼

1. An integrated circuit, comprising: a substrate of the integrated circuit; and foamed parylene material on at least a portion of the substrate. 2. The integrated circuit of claim 1, wherein the foamed parylene material has a maximum cell size of less than about 3.0 microns.3. The integrated

1. An integrated circuit, comprising: a substrate of the integrated circuit; and foamed parylene material on at least a portion of the substrate. 2. The integrated circuit of claim 1, wherein the foamed parylene material has a maximum cell size of less than about 3.0 microns.3. The integrated circuit of claim 2, wherein the foamed parylene material has a maximum cell size of less than about 1.0 micron.4. The integrated circuit of claim 3, wherein the foamed parylene material has a maximum cell size of less than about 0.1 micron.5. The integrated circuit of claim 1, further comprising a conductive layer adjacent the foamed parylene material.6. The integrated circuit of claim 5, wherein the conductive layer comprises a metal line on the foamed parylene material.7. The integrated circuit of claim 5, wherein the conductive layer comprises an interconnect selected from the group consisting of a contact and a via adjacent the foamed parylene material.8. An integrated circuit, comprising: a first conductive layer; a second conductive layer; and foamed parylene material between the first conductive layer and the second conductive layer in the integrated circuit, wherein a cell size of the foamed parylene material is less than a distance between the first and second conductive layers. 9. The integrated circuit of claim 8, wherein the foamed parylene material has a maximum cell size of less than about 3.0 microns.10. The integrated circuit of claim 9, wherein the foamed parylene material has a maximum cell size of less than about 1.0 micron.11. The integrated circuit of claim 10, wherein the foamed parylene material has a maximum cell size of less than about 0.1 micron.