이 특허에 인용된 특허 (35) 인용/피인용 타임라인 분석

1. Hideyuki Kurita JP; Masahiro Fujimoto JP, BGA package substrate.

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2. Chittipeddi Sailesh ; Ryan Vivian, Bond pad for a flip chip package, and method of forming the same.

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3. Chittipeddi Sailesh ; Ryan Vivian, Bond pad for a flip-chip package.

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4. Itai Motohiko,JPX ; Hashimoto Hiroyuki,JPX ; Kimura Kazuo,JPX, Ceramic substrate having pads to be attached to terminal members with Pb-Sn solder and method of producing the same.

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5. Ference Thomas George ; Howell Wayne John ; Sprogis Edmund Juris, Chip-on-chip interconnections of varied characteristics.

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6. Ishino Masakazu,JPX ; Satoh Ryohei,JPX ; Mita Mamoru,JPX, Electrode structure of a wiring substrate of semiconductor device having expanded pitch.

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7. Wong Kaiser H., Fine flip chip interconnection.

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8. Richard H. Estes ; James E. Clayton ; Koji Ito JP; Masanori Akita JP; Toshihiro Mori JP; Minoru Wada JP, Flip chip mounting technique.

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9. Ying-Chou Tsai TW; Shih-Kuang Chiu TW; Kuo-Liang Mao TW; Chao-Dung Suo TW, Flip-chip bonding structure on substrate for flip-chip package application.

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10. Bodo Peter,SEX ; Hesselbom Hjalmar,SEX ; Hentzell Hans,SEX, Flip-chip type connection with elastic contacts.

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11. Ho Chung W., High density flip chip BGA.

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12. Carpenter Charles (Poughkeepsie NY) Fugardi Joseph F. (Wappingers Falls NY) Gregor Lawrence V. (Hopewell Junction NY) Grosewald Peter S. (Putnam Valley NY) Reeber Morton D. (Shrub Oak NY), Improved solder interconnection between a semiconductor device and a supporting substrate.

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13. Dedert Ronald J. ; Hollinger ; Jr. William A. ; Kaverman Paul J., Integrated circuit anti-bridging leads design.

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14. Marrs Robert C., Integrated circuit chip to substrate interconnection.

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15. Marrs Robert C., Integrated circuit chip to substrate interconnection and method.

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16. Boyko Christina M. ; Ingraham Anthony P. ; Markovich Voya R. ; Russell David J., Interconnect structure for joining a chip to a circuit card.

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17. Darveaux Robert F. ; Miles Barry M. ; Copia Alexander W., Making solder ball mounting pads on substrates.

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18. Farnworth Warren M., Mask repattern process.

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19. Edwards Darvin R., Method and apparatus for attaching particles to a substrate.

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20. Wachtler Kurt P. ; Hotchkiss Gregory B., Method and apparatus for the attachment of particles to a substrate.

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21. LaFontaine ; Jr. William Rena ; Mescher Paul Allen ; Woychik Charles Gerard, Method for joining a semiconductor chip to a chip carrier substrate and resulting chip package.

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22. Dery Jean,CAX ; Egitto Frank D. ; Matienzo Luis J. ; Ouellet Charles,CAX ; Ouellet Luc,CAX ; Questad David L. ; Rudik William J. ; Tran Son K., Method of forming a flip chip assembly.

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23. Wael Zohni, Off-center solder ball attach and methods therefor.

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24. Maeno Yoshinobu,JPX ; Abe Kenichiro,JPX ; Soekawa Kouzi,JPX, Packaging structure for a semiconductor element flip-chip mounted on a mounting board having staggered bump connection location on the pads and method thereof.

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25. Sawairi Hitoshi (Hirakata JPX) Hirose Fuminori (Hirakata JPX) Konishikawa Kaoru (Hirakata JPX), Printed circuit board.

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26. Schtt Joachim (Neusss DEX), Printed circuit board having tapered contact pads for surface mounted electrical components.

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27. Frankoski Edward Jay ; Memis Irving, Printed circuit boards for mounting a semiconductor integrated circuit die.

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28. Lewis Robert Lee ; Sebesta Robert David ; Waits Daniel Martin, Process for connecting an electrical device to a circuit substrate.

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29. Nakanishi Teru (Kawasaki JPX) Karasawa Kazuaki (Kawasaki JPX) Ochiai Masayuki (Kawasaki JPX) Hashimoto Kaoru (Kawasaki JPX), Process for flip chip connecting a semiconductor chip.

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30. Jimarez Miguel Angel ; Neira Reinaldo Anthony, Receptor pad structure for chip carriers.

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31. Nakamura, Akio, Semiconductor device with staggered hexagonal electrodes and increased wiring width.

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32. Rostoker Michael D. (San Jose CA) Heim Dorothy A. (San Jose CA), Semiconductor die having a high density array of composite bond pads.

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33. Tanaka Kei,JPX, Structure for bonding semiconductor device to substrate.

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34. Visel Thomas A. (Phoenix AZ) Long Jon M. (Livermore CA), System for securing and electrically connecting a semiconductor chip to a substrate.

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35. Rostoker Michael D. (San Jose CA), Technique of increasing bond pad density on a semiconductor die.

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이 특허를 인용한 특허 (10) 인용/피인용 타임라인 분석

1. Cai, Yuhong; Guo, Mao, Ball pad with a plurality of lobes.

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2. Araki, Yasushi; Sato, Seiji; Nakamura, Masatoshi; Ozawa, Takashi, Flip-chip mounting substrate and flip-chip mounting method.

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3. Yeduru, Srinivasa Reddy; Gasser, Karl Heinz; Woehlert, Stefan; Mayer, Karl; Santos Rodriguez, Francisco Javier, Method for processing a wafer and wafer structure.

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4. Cubero Pitel, Jose Antonio; Fores Montserrat, Andreu; Torrijos Ezquerra, Maria Leonor, Method for producing a printed circuit board.

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5. Lee, Doo-Hwan; Kim, Seung-Gu; Bae, Won-Cheol; Kim, Moon-Il; Lee, Jae-Kul, Method of manufacturing a component-embedded printed circuit board.

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6. Kondo,Koji; Kataoka,Ryohei; Yokochi,Tomohiro; Nakagoshi,Makoto; Murai,Tadashi; Hayashi,Akimori; Suzuki,Katsunobu, Printed circuit board having colored outer layer.

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7. Wang, Yu-Po; Huang, Chien-Ping; Lin, Wei-Chun; Lee, Wen Cheng, Semiconductor package substrate.

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8. Reiss,Martin; Bender,Carsten; Nocke,Kerstin, Substrate for producing a soldering connection.

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9. Gambino, Jeffrey P.; Leidy, Robert K.; Rassel, Richard J., Thick bond pad for chip with cavity package.

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10. Gambino, Jeffrey P.; Leidy, Robert K.; Rassel, Richard J., Thick bond pad for chip with cavity package.

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