IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0509486
(2000-03-29)
|
우선권정보 |
JP-0302182 (1997-11-04) |
국제출원번호 |
PCT/JP98/04704
(1998-10-16)
|
국제공개번호 |
WO99/23777
(1999-05-14)
|
발명자
/ 주소 |
|
출원인 / 주소 |
|
대리인 / 주소 |
Birch, Stewart, Kolasch & Birch, LLP
|
인용정보 |
피인용 횟수 :
4 인용 특허 :
5 |
초록
▼
A multi-rated delay multiplexing direct spread spectrum communication system the multiplicity of which can be changed. The system performs control operation as quickly as possible by suppressing the output fluctuation within a narrow range so as to perform constant power transmission. A gain-variabl
A multi-rated delay multiplexing direct spread spectrum communication system the multiplicity of which can be changed. The system performs control operation as quickly as possible by suppressing the output fluctuation within a narrow range so as to perform constant power transmission. A gain-variable amplifier is provided at the succeeding stage of a modulator and the gain of the amplifier is controlled by a control signal generated based on the detection signal of the output of a power amplifying section. A detecting and control section detects the RF output of a delay multiplexing spread signal by a diode, finds the average power by an integrator, and equalizes the output of the amplifier to a comparation voltage by a control signal which is generated on comparing the average power with the comparation voltage. However, when the output of the amplifier is equalized to the comparation voltage, the time constant of the integration performed by the section is kept small for a fixed period of time by using a control signal representing a simplex/multiplex part. Consequently, a multiplexing switching section can quickly control the power.
대표청구항
▼
A multi-rated delay multiplexing direct spread spectrum communication system the multiplicity of which can be changed. The system performs control operation as quickly as possible by suppressing the output fluctuation within a narrow range so as to perform constant power transmission. A gain-variabl
A multi-rated delay multiplexing direct spread spectrum communication system the multiplicity of which can be changed. The system performs control operation as quickly as possible by suppressing the output fluctuation within a narrow range so as to perform constant power transmission. A gain-variable amplifier is provided at the succeeding stage of a modulator and the gain of the amplifier is controlled by a control signal generated based on the detection signal of the output of a power amplifying section. A detecting and control section detects the RF output of a delay multiplexing spread signal by a diode, finds the average power by an integrator, and equalizes the output of the amplifier to a comparation voltage by a control signal which is generated on comparing the average power with the comparation voltage. However, when the output of the amplifier is equalized to the comparation voltage, the time constant of the integration performed by the section is kept small for a fixed period of time by using a control signal representing a simplex/multiplex part. Consequently, a multiplexing switching section can quickly control the power. al., 381/043; US-5133013, 19920700, Munday, 381/047; US-5249205, 19930900, Chennakeshu et al., 375/348; US-5373098, 19941200, Kitayama et al., 084/659; US-5400151, 19950300, Okada, 358/340; US-5498998, 19960300, Gehrke et al., 331/017; US-5651071, 19970700, Lindemann et al., 381/068.2; US-5727072, 19980300, Raman, 381/094.2 ed to the first output of said first synchronization sub-circuit, a second combiner input coupled to the second output of said second synchronization sub-circuit, and a combiner output, said combiner combining said individual data pulses after processing by said first and second synchronization sub-circuits to generate a synchronous signal at the said combiner output, such that said synchronous signal is representative of said individual data pulses of said asynchronous signal. 3. The synchronization circuit of claim 2, wherein said selector comprises a selector flip-flop having a clock input for coupling to said asynchronous signal, a non-inverted first selector output coupled to the second input of said first synchronization sub-circuit, an inverted second selector output coupled to the fourth input of said second synchronization sub-circuit, and a selector input coupled to the inverted output of said selector flip-flop, such that said selector flip-flop detects said individual data pulses of said asynchronous signal and alternately selects said first and second synchronization sub-circuits to process said individual data pulses.4. The synchronization circuit of claim 3, wherein each of said first and second synchronization sub-circuits comprises: a first supplementary flip-flop having an output, a low clear input, a rising-edge clock input coupled to said asynchronous signal, and a data input coupled to said selector flip-flop of said selector circuit, wherein the data input of said first supplementary flip-flop of said first synchronization sub-circuit is coupled to the output of said selector flip-flop and the data input of said second flip-flop of said second synchronization sub-circuit is coupled to the inverted output of said selector flip-flop; a second supplementary flip-flop having an output, a low clear input, a data input coupled to the output of said second flip-flop, and a falling-edge clock input operably coupled to said clock; a third supplementary flip-flop having a non-inverted output, an inverted output coupled to the low clear input of said third flip-flop, a data input coupled to the output of said third flip-flop, and a rising-edge clock input operably coupled to said clock; and a NAND gate having a first input for coupling to said clock, a second input coupled to the output of said third supplementary flip-flop, and an output coupled to the low clear input of the first supplementary flip-flop. 5. The synchronization circuit of claim 4, wherein said combiner is an OR gate.6. The synchronization circuit of claim 5, wherein all flip-flops are D-type flip-flops.7. The synchronization circuit of claim 3, wherein each of said first and second synchronization sub-circuits comprises: a first supplementary flip-flop having an output, a clear input, a clock input coupled to said asynchronous signal, and a data input coupled to said first flip-flop of said selector circuit, wherein the data input of said first supplementary flip-flop of said first synchronization sub-circuit is coupled to the output of said selector flip-flop of said selector circuit and the data input of said first supplementary flip-flop of said second synchronization sub-circuit is coupled to the inverted output of said selector flip-flop; a second supplementary flip-flop having an output, a clear input, a data input coupled to the output of said first supplementary flip-flop, and a clock input operably coupled to said clock; a third supplementary flip-flop having a non-inverted output, an inverted output coupled to the clear input of said second supplementary flip-flop, a data input coupled to the output of said second supplementary flip-flop, and a clock input operably coupled to said clock; and a NAND gate having a first input for coupling to said clock, a second input coupled to the output of said third supplementary flip-flop, and an output coupled to the clear input of said first supplementary flip-flop. 8. The sync
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