[특허]Network presence indicator for communications management

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-015/177
출원번호	US-0137688 (1998-08-21)
발명자 / 주소	Brisebois, Michel A. Ryan, Desmond J. French-St. George, Marilyn Mahan, Laura Johnson, John I. Roberts, Jobe L. W.
출원인 / 주소	Nortel Networks Limited
대리인 / 주소	Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
인용정보	피인용 횟수 : 36 인용 특허 : 15

초록 ▼

To provide telephony-like interfaces to a computer network, a computer system has a visual display device that continually displays a network status icon indicating network status information. The icon can have segments corresponding to different communications environments, and the icon and the seg

To provide telephony-like interfaces to a computer network, a computer system has a visual display device that continually displays a network status icon indicating network status information. The icon can have segments corresponding to different communications environments, and the icon and the segments will change some characteristic, such as shape, size, or color, to indicate the presence of some network event or the status of some network parameter.

대표청구항 ▼

To provide telephony-like interfaces to a computer network, a computer system has a visual display device that continually displays a network status icon indicating network status information. The icon can have segments corresponding to different communications environments, and the icon and the seg

To provide telephony-like interfaces to a computer network, a computer system has a visual display device that continually displays a network status icon indicating network status information. The icon can have segments corresponding to different communications environments, and the icon and the segments will change some characteristic, such as shape, size, or color, to indicate the presence of some network event or the status of some network parameter. bit source-destination address holds a packed data having 128 bits.9. The digital processing apparatus recited in claim 8 wherein the packed shift control signal format comprises a second byte and a third byte in addition to the first byte permitting an operation code to specify a packed shift operation to perform an arithmetic right shift of word elements, doubleword elements or quadword elements from the first packed data.10. The digital processing apparatus recited in claim 8 wherein the packed shift control signal format comprises a second byte and a third byte in addition to the first byte permitting an operation code to specify a packed shift operation to perform a logical shift of word elements, doubleword elements or quadword elements from the first packed data.11. The digital processing apparatus recited in claim 10 wherein the fourth byte of the five or more bytes is further permitting a three-bit operation code extension to specify a packed shift operation to perform a logical shift of double quadword elements from the first packed data.12. The digital processing apparatus recited in claim 7 wherein the fourth byte of the four or more bytes is further permitting a three-bit operation code extension to indicate that the first packed shift operation is a packed shift immediate operation.13. The digital processing apparatus recited in claim 12 wherein the fourth byte of the four or more bytes is permitting the three-bit operation code extension to also indicate that the positions of the first number of positions are byte positions.14. The digital processing apparatus of claim 13 wherein the first replacement data generated for one of the first number of positions represents a value of zero.15. The digital processing apparatus of claim 12 wherein the packed shift control signal format further comprises a fifth byte, indicated as the shift count source for an immediate shift count.16. A processor comprising: a storage location to hold a packed data having M times N bits; a decoder to receive a first control signal of a first control signal format and a second control signal of a second control signal format, the decoder to identify a first shift operation, and a first count less than or equal to M corresponding to the first control signal and to identify a second shift operation, and a second count less than or equal to N corresponding to the second control signal; and a functional unit to shift the packed data by the first count of first positions and generate a first replacement data for one of the first positions responsive to the first shift operation being identified, and to shift the packed data by a second count of second positions generate a second replacement data for one of the second positions responsive to the second shift operation being identified, the functional unit further to produce a shifted packed data comprising the first replacement data responsive to the first shift operation being identified and to produce a shifted packed data comprising the second replacement data responsive to the second shift operation being identified. 17. The processor of claim 16 wherein the second positions are byte positions.18. The processor of claim 17 wherein M is eight.19. The processor of claim 17 wherein M is sixteen.20. The processor of claim 19 wherein the first positions are bit positions.21. The processor of claim 16 wherein the second positions are pixel positions.22. The processor of claim 16 wherein the second positions are voxel positions.23. An apparatus comprising: a first storage area to store packed data, the first storage area representing a register in a first set of architectural registers; a decoder to decode control signals of a first set of control signal formats; shifting logic to shift a first plurality of packed data stored in the first storage area by a number of shift positions responsive to the decoding of a control signal of the first set of control signal formats; and

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이 특허에 인용된 특허 (15) 인용/피인용 타임라인 분석

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Archibong, Ime; Badros, Gregory Joseph; Campbell, Colin Cameron Brennan; Garcia, David Harry; Heynen, Mark; Krausz, Brian; Marlow, Cameron Alexander; Shaffer, Justin Alexander; Toksvig, Michael John McKenzie; Tseng, Erick; Wong, Yong Kean, Sharing television and video programming through social networking.
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