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A method and apparatus for encoding and decoding data. A primary data channel comprising a parallel data word has a bit of a secondary data channel associated with the parallel data word. ECC bits are generated based upon the parallel data word and the monitor bit and the ECC bits are appended to th

A method and apparatus for encoding and decoding data. A primary data channel comprising a parallel data word has a bit of a secondary data channel associated with the parallel data word. ECC bits are generated based upon the parallel data word and the monitor bit and the ECC bits are appended to the data comprising the primary and secondary channel data to form an extended width parallel word. The extended width parallel data word is divided into a plurality of lesser width data words which are each scrambled using respective side scrambler for form respective cipher data words. An ECC control bit and a parity bit is generated for each channel, and associated with the cipher data words to form extended cipher data words. The cipher data words are serialized and transmitted over a serial link. The received serial data is deserialized, word framed and word aligned across the respective channels, and descrambled to obtain the data contained in the primary and secondary data channels. ECC is provided both on data and control bits to permit error correction on either the data or control information.

대표청구항 ▼

A method and apparatus for encoding and decoding data. A primary data channel comprising a parallel data word has a bit of a secondary data channel associated with the parallel data word. ECC bits are generated based upon the parallel data word and the monitor bit and the ECC bits are appended to th

A method and apparatus for encoding and decoding data. A primary data channel comprising a parallel data word has a bit of a secondary data channel associated with the parallel data word. ECC bits are generated based upon the parallel data word and the monitor bit and the ECC bits are appended to the data comprising the primary and secondary channel data to form an extended width parallel word. The extended width parallel data word is divided into a plurality of lesser width data words which are each scrambled using respective side scrambler for form respective cipher data words. An ECC control bit and a parity bit is generated for each channel, and associated with the cipher data words to form extended cipher data words. The cipher data words are serialized and transmitted over a serial link. The received serial data is deserialized, word framed and word aligned across the respective channels, and descrambled to obtain the data contained in the primary and secondary data channels. ECC is provided both on data and control bits to permit error correction on either the data or control information. t (DC) level; anda second bias circuit electrically coupled to the second input terminal of the signal detector and adapted to bias the digital pulse signal at a second predetermined DC level different from the first predetermined DC level,wherein a DC difference between the first predetermined DC level and the second predetermined DC level is less than the predetermined amplitude of the digital pulse signal electrically coupled to the one of the first input terminal and the second input terminal of the signal detector that is not electrically coupled to the first terminal of the pushbutton switch,wherein a first difference exists between the predetermined amplitude of a first one of the digital pulse signal received at the first terminal of the signal detector and the digital pulse signal received at the second terminal of the signal detector and the predetermined amplitude of a second different one of the digital pulse signal received at the first terminal of the signal detector and the digital pulse signal received at the second terminal of the signal detector responsive to the pushbutton switch not being actuated,wherein a second difference exists between the predetermined amplitude the first one of the digital pulse signal received at the first terminal of the signal detector and the digital pulse signal received at the second terminal of the signal detector and the predetermined amplitude of the second different one of the digital pulse signal received at the first terminal of the signal detector and the digital pulse signal received at the second terminal of the signal detector responsive to the pushbutton switch being actuated, andwherein the output terminal of the signal detector generates an output signal having a first level and a second level, different from the first level, wherein the first level is generated responsive to the first difference causing the electronic system to remain in a low power consumption mode, and wherein the second level is generated responsive to the second difference causing the electronic system to transition from the low power consumption mode to a normal power consumption mode.2. A wake-up circuit according to claim 1 wherein the signal detector further comprises: a comparator. 3. A wake-up circuit according to claim 1 wherein the first bias circuit further comprises: a first resistor divider circuit having a first resistor and a second resistor, wherein each of the first resistor and the second resistor of the first bias circuit have a first terminal and a second terminal, wherein the first terminal of the first resistor is electrically coupled to the power supply, wherein the second terminal of the first resistor is electrically coupled to the first terminal of the second resistor and electrically coupled to the first input terminal of the signal detector, and wherein the second terminal of the second resistor is electrically coupled to a ground potential. 4. A wake-up circuit according to claim 1 wherein the second bias circuit further comprises: a second resistor divider circuit having a third resistor and a fourth resistor, wherein each of the third resistor and the fourth resistor of the second bias circuit have a first terminal and a second terminal, wherein the first terminal of the third resistor is electrically coupled to the output terminal of the signal generator, wherein the second terminal of the third resistor is electrically coupled to the first terminal of the fourth resistor and electrically coupled to the second input terminal of the signal detector, and wherein the second terminal of the fourth resistor is electrically coupled to the ground potential. 5. A wake-up circuit according to claim 1 further comprising: a capacitor having a first terminal and a second terminal, wherein the first terminal is electrically coupled to the ground potential, wherein the second terminal is electrically coupled to the output terminal of the signal detector, wherein the capac itor is adapted to increase an amount of time that the second level of the output signal is present to provide a lengthened second level of the output signal, and wherein the lengthened second level of the output signal permits the electronic system to transition from the low power consumption mode to the normal power consumption mode. 6. A wake-up circuit for an electronic system, comprising: a signal generator having an output terminal and adapted to generate a digital pulse signal at the output terminal, wherein the digital pulse signal has a predetermined amplitude and a predetermined duration, wherein the output terminal of the signal generator is electrically coupled to a first terminal of a pushbutton switch having a second terminal electrically coupled to a ground potential; a comparator having a power supply terminal, a ground terminal, a first input terminal, a second input terminal and an output terminal, wherein the power supply terminal is adapted to receive power from a power supply, wherein the ground terminal is adapted to be electrically coupled to the ground potential, wherein each of the first input terminal and the second input terminal of the comparator are adapted to receive the digital pulse signal, wherein one of the first input terminal and the second input terminal of the comparator is electrically coupled to the first terminal of the pushbutton switch, and wherein the comparator further comprises: a first bias circuit electrically coupled to the first input terminal of the comparator and adapted to bias the digital pulse signal at a first predetermined direct current (DC) level, wherein the first bias circuit further includes:a first resistor divider circuit having a first resistor and a second resistor, wherein each of the first resistor and the second resistor of the first bias circuit have a first terminal and a second terminal, wherein the first terminal of the first resistor is electrically coupled to the power supply, wherein the second terminal of the first resistor is electrically coupled to the first terminal of the second resistor and electrically coupled to the first input terminal of the comparator,-and wherein the second terminal of the second resistor is electrically coupled to a ground potential; anda second bias circuit electrically coupled to the second input terminal of the comparator and adapted to bias the digital pulse signal at a second predetermined DC level different from the first predetermined DC level, wherein the second bias circuit further includes:a second resistor divider circuit having a third resistor and a fourth resistor, wherein each of the third resistor and the fourth resistor of the second bias circuit have a first terminal and a second terminal, wherein the first terminal of the third resistor is electrically coupled to the output terminal of the signal generator, wherein the second terminal of the third resistor is electrically coupled to the first terminal of the fourth resistor and electrically coupled to the second input terminal of the comparator, and wherein the second terminal of the fourth resistor is electrically coupled to the ground potential,wherein a DC difference between the first predetermined DC level and the second predetermined DC level is less than the predetermined amplitude of the digital pulse signal electrically coupled to the one of the first input terminal and the second input terminal of the comparator that is not electrically coupled to the first terminal of the pushbutton switch,wherein a first difference exists between the predetermined amplitude a first one of the digital pulse signal received at the first terminal of the comparator and the digital pulse signal received at the second terminal of the signal detector and the predetermined amplitude of a second different one of the digital pulse signal received at the first terminal of the signal detector and the digital pulse signal received at the second terminal of the compa rator responsive to the pushbutton switch not being actuated,wherein a second difference exists between the predetermined amplitude the first one of the digital pulse signal received at the first terminal of the comparator and the digital pulse signal received at the second terminal of the signal detector and the predetermined amplitude of the second different one of the digital pulse signal received at the first terminal of the signal detector and the digital pulse signal received at the second terminal of the comparator responsive to the pushbutton switch being actuated, andwherein the output terminal of the comparator generates an output signal having a first level and a second level, different from the first level, wherein the first level is generated responsive to the first difference causing the electronic system to remain in a low power consumption mode, and wherein the second level is generated responsive to the second difference causing the electronic system to transition from the low power consumption mode to a normal power consumption mode.7. A wake-up circuit according to claim 1 further comprising: a capacitor having a first terminal and a second terminal, wherein the first terminal is electrically coupled to the ground potential, wherein the second terminal is electrically coupled to the output terminal of the comparator, wherein the capacitor is adapted to increase an amount of time that the second level of the output signal is present to provide a lengthened second level of the output signal, and wherein the lengthened second level of the output signal permits the electronic system to transition from the low power consumption mode to the normal power consumption mode. 8. A telematics control unit for a telematics communications system, comprising: a standby mode power supply electrically coupled to a battery and adapted to operate in a low power consumption mode; a normal mode power supply electrically coupled to the battery and adapted to operate in a normal power consumption mode; and a wake-up circuit including: a signal generator having an output terminal and adapted to generate a digital pulse signal at the output terminal, wherein the digital pulse signal has a predetermined amplitude and a predetermined duration, wherein the output terminal of the signal generator is electrically coupled to a first terminal of a pushbutton switch having a second terminal electrically coupled to a ground potential; a signal detector having a power supply terminal, a ground terminal, a first input terminal, a second input terminal and an output terminal, wherein the power supply terminal is adapted to receive power from a power supply, wherein the ground terminal is adapted to be electrically coupled to the ground potential, wherein each of the first input terminal and the second input terminal of the signal detector are adapted to receive the digital pulse signal, wherein one of the first input terminal and the second input terminal of the signal detector is electrically coupled to the first terminal of the pushbutton switch, and wherein the signal detector further comprises: a first bias circuit electrically coupled to the first input terminal of the signal detector and adapted to bias the digital pulse signal at a first predetermined direct current (DC) level; anda second bias circuit electrically coupled to the second input terminal of the signal detector and adapted to bias the digital pulse signal at a second predetermined DC level different from the first predetermined DC level,wherein a DC difference between the first predetermined DC level and the second predetermined DC level is less than the predetermined amplitude of the digital pulse signal electrically coupled to the one of the first input terminal and the second input terminal of the signal detector that is not electrically coupled to the first terminal of the pushbutton switch,wherein a first difference exists between the predetermined amplitud