초록 ▼

A MOSFET device and method of fabricating are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a MOSFET device structure to eliminate the requirement for halo/pocket implants and shallow source/drain extensions to c

A MOSFET device and method of fabricating are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a MOSFET device structure to eliminate the requirement for halo/pocket implants and shallow source/drain extensions to control short channel effects. Additionally, the present invention unconditionally eliminates the parasitic bipolar gain associated with MOSFET fabrication, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art.

대표청구항 ▼

1. A CMOS circuit comprising: at least one Schottky barrier NMOS and Schottky barrier PMOS devices; the Schottky barrier NMOS and Schottky barrier PMOS devices each comprising: channel dopants in a semiconductor substrate such that dopant concentration varies significantly in a vertical direct

1. A CMOS circuit comprising: at least one Schottky barrier NMOS and Schottky barrier PMOS devices; the Schottky barrier NMOS and Schottky barrier PMOS devices each comprising: channel dopants in a semiconductor substrate such that dopant concentration varies significantly in a vertical direction of the semiconductor substrate and is generally constant in a lateral direction of the semiconductor substrate;a gate electrode on the semiconductor substrate; anda source electrode and a drain electrode on the semiconductor substrate defining a channel having a channel length being less than or equal to 100 nm, wherein at least one of the source electrode and the drain electrode forms a Schottky or Schottky-like contact to the semiconductor substrate.2. The circuit of claim 1 wherein the source electrode and the drain electrode of the Schottky barrier PMOS device are formed from a member of the group consisting of: Platinum Suicide, Palladium Silicide and Iridium Silicide.3. The circuit of claim 1 wherein the source electrode and the drain electrode of the Schottky barrier NMOS device are formed from a member of the group consisting of rare-earth suicides.4. The circuit of claim 1 wherein at least one of the source and drain electrodes of the Schottky barrier PMOS devices forms a Schottky or Schottky-like contact with the semiconductor substrate at least in areas adjacent to the channel.5. The circuit of claim 1 wherein at least one of the source and drain electrodes of the Schottky barrier NMOS devices forms a Schottky or Schottky-like contact with the semiconductor substrate at least in areas adjacent to the channel.6. The circuit of claim 2 wherein an entire interface between at least one of the source and the drain electrodes of the Schottky barrier PMOS device and the semiconductor substrate forms a Schottky contact or Schottky-like region with the semiconductor substrate.7. The circuit of claim 1 wherein an entire interface between at least one of the source and the drain electrodes of the Schottky barrier NMOS device and the semiconductor substrate forms a Schottky contact or Schottky-like region with the semiconductor substrate.8. The circuit of claim 1 wherein the channel dopants for the Schottky barrier PMOS device are selected from the group consisting of: Arsenic, Phosphorous, and Antimony.9. The circuit of claim 1 wherein the channel dopants for the Schottky barrier NMOS device are selected from the group consisting of Boron, Indium, and Gallium.10. The circuit of claim 1 wherein the gate electrode of the Schottky barrier NMOS device has a length not exceeding 100 nm.11. The circuit of claim 1 wherein the gate electrode of the Schottky barrier PMOS device has a length not exceeding 100 nm.12. The circuit of claim 1 wherein the gate electrode of at least one of the Schottky barrier NMOS and Schottky barrier PMOS devices comprises: an insulating layer on the semiconductor substrate; a conducting film on the insulating layer; and at least one insulating layer on at least one sidewall of the conducting film. 13. The circuit of claim 12 wherein the Schottky barrier NMOS device has a gate electrode conducting film comprised of phosphorous doped polysilicon.14. The circuit of claim 12 wherein the Schottky barrier PMOS device has a gate electrode conducting film comprised of boron doped polysilicon.15. The circuit of claim 12 wherein the Schottky barrier PMOS device has a gate electrode conducting film comprised of boron doped polysilicon.16. The circuit of claim 1, wherein the circuit further comprises at least one NMOS device having an impurity doped source and drain electrode.17. The circuit of claim 1, wherein the circuit further comprises at least one PMOS device having an impurity doped source and drain electrode.18. A CMOS circuit comprising: at least one Schottky barrier NMOS and Schottky barrier PMOS devices; the Schottky barrier NMOS device and Schottky barrier PMOS device each comprising: channel d opants in a semiconductor substrate such that dopant concentration varies significantly in a vertical direction of the semiconductor substrate and is generally constant in a lateral direction of the semiconductor substrate;a gate electrode on the semiconductor substrate; anda source electrode and a drain electrode on the semiconductor substrate defining a channel such that a length of the channel is less than or equal to 100 nm, wherein at least one of the source electrode and the drain electrode forms a Schottky or Schottky-like contact with the semiconductor substrate; wherein the source electrode and the drain electrode of the Schottky barrier PMOS device are formed from a member of the group consisting of: Platinum Suicide, Palladium Silicide and Iridium Silicide; wherein the source electrode and the drain electrode of the Schottky barrier NMOS device are formed from a member of the group consisting of rare-earth silicides; wherein at least one of the source and drain electrodes of the Schottky barrier PMOS devices forms a Schottky or Schottky-like contact with the semiconductor substrate at least in areas adjacent to the channel; wherein at least one of the source and drain electrodes of the Schottky barrier NMOS devices forms a Schottky or Schottky-like contact with the semiconductor substrate at least in areas adjacent to the channel; wherein the channel dopants for the Schottky barrier PMOS devices are selected from the group consisting of: Arsenic, Phosphorous, and Antimony; wherein the channel dopants for the Schottky barrier NMOS devices are selected from the group consisting of: Boron, Indium, and Gallium; wherein the gate electrode of the Schottky barrier NMOS device has a length not exceeding 100 nm; wherein the gate electrode of the Schottky barrier PMOS device has a length not exceeding 100 nm; wherein the gate electrode of the Schottky barrier NMOS and Schottky barrier PMOS devices comprises: an insulating layer on the semiconductor substrate;a conducting film on the insulating layer; andat least one insulating layer on at least one sidewall of the conducting film; wherein the Schottky barrier NMOS device has a gate electrode conducting film comprising phosphorous doped polysilicon; wherein the Schottky barrier PMOS device has a gate electrode conducting film comprising boron doped polysilicon.